/* SPDX-License-Identifier: GPL-2.0
 * aw882xx_pid_2113_reg.h
 *
 * Copyright (c) 2020 AWINIC Technology CO., LTD
 *
 * Author: Nick Li <liweilei@awinic.com.cn>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#ifndef __AW882XX_PID_2113_REG_H__
#define __AW882XX_PID_2113_REG_H__

#define AW_PID_2113_MONITOR_FILE	"aw882xx_pid_2113_monitor.bin"

/* registers list */
#define AW_PID_2113_ID_REG		(0x00)
#define AW_PID_2113_SYSST_REG		(0x01)
#define AW_PID_2113_SYSINT_REG		(0x02)
#define AW_PID_2113_SYSINTM_REG		(0x03)
#define AW_PID_2113_SYSCTRL_REG		(0x04)
#define AW_PID_2113_SYSCTRL2_REG	(0x05)
#define AW_PID_2113_I2SCTRL1_REG	(0x06)
#define AW_PID_2113_I2SCTRL2_REG	(0x07)
#define AW_PID_2113_I2SCTRL3_REG	(0x08)
#define AW_PID_2113_DACCFG1_REG		(0x09)
#define AW_PID_2113_DACCFG2_REG		(0x0A)
#define AW_PID_2113_DACCFG3_REG		(0x0B)
#define AW_PID_2113_DACCFG4_REG		(0x0C)
#define AW_PID_2113_DACCFG5_REG		(0x0D)
#define AW_PID_2113_DACCFG6_REG		(0x0E)
#define AW_PID_2113_DACCFG7_REG		(0x0F)
#define AW_PID_2113_DACCFG8_REG		(0x10)
#define AW_PID_2113_PWMCTRL1_REG	(0x11)
#define AW_PID_2113_PWMCTRL2_REG	(0x12)
#define AW_PID_2113_I2SCFG1_REG		(0x13)
#define AW_PID_2113_DBGCTRL_REG		(0x14)
#define AW_PID_2113_DACCFG9_REG		(0x15)
#define AW_PID_2113_DACCFG10_REG	(0x16)
#define AW_PID_2113_DACST_REG		(0x20)
#define AW_PID_2113_VBAT_REG		(0x21)
#define AW_PID_2113_TEMP_REG		(0x22)
#define AW_PID_2113_PVDD_REG		(0x23)
#define AW_PID_2113_ISNDAT_REG		(0x24)
#define AW_PID_2113_VSNDAT_REG		(0x25)
#define AW_PID_2113_I2SINT_REG		(0x26)
#define AW_PID_2113_I2SCAPCNT_REG	(0x27)
#define AW_PID_2113_ANASTA1_REG		(0x28)
#define AW_PID_2113_ANASTA2_REG		(0x29)
#define AW_PID_2113_ANASTA3_REG		(0x2A)
#define AW_PID_2113_TESTDET_REG		(0x2B)
#define AW_PID_2113_DSMCFG1_REG		(0x30)
#define AW_PID_2113_DSMCFG2_REG		(0x31)
#define AW_PID_2113_DSMCFG3_REG		(0x32)
#define AW_PID_2113_DSMCFG4_REG		(0x33)
#define AW_PID_2113_DSMCFG5_REG		(0x34)
#define AW_PID_2113_DSMCFG6_REG		(0x35)
#define AW_PID_2113_DSMCFG7_REG		(0x36)
#define AW_PID_2113_DSMCFG8_REG		(0x37)
#define AW_PID_2113_TESTIN_REG		(0x38)
#define AW_PID_2113_TESTOUT_REG		(0x39)
#define AW_PID_2113_SADCCTRL1_REG	(0x3A)
#define AW_PID_2113_SADCCTRL2_REG	(0x3B)
#define AW_PID_2113_SADCCTRL3_REG	(0x3C)
#define AW_PID_2113_SADCCTRL4_REG	(0x3D)
#define AW_PID_2113_SADCCTRL5_REG	(0x3E)
#define AW_PID_2113_SADCCTRL6_REG	(0x3F)
#define AW_PID_2113_SADCCTRL7_REG	(0x40)
#define AW_PID_2113_VSNTM1_REG		(0x50)
#define AW_PID_2113_VSNTM2_REG		(0x51)
#define AW_PID_2113_ISNCTRL1_REG	(0x52)
#define AW_PID_2113_ISNCTRL2_REG	(0x53)
#define AW_PID_2113_PLLCTRL1_REG	(0x54)
#define AW_PID_2113_PLLCTRL2_REG	(0x55)
#define AW_PID_2113_PLLCTRL3_REG	(0x56)
#define AW_PID_2113_CDACTRL1_REG	(0x57)
#define AW_PID_2113_CDACTRL2_REG	(0x58)
#define AW_PID_2113_DITHERCFG1_REG	(0x59)
#define AW_PID_2113_DITHERCFG2_REG	(0x5A)
#define AW_PID_2113_DITHERCFG3_REG	(0x5B)
#define AW_PID_2113_CPCTRL_REG		(0x5C)
#define AW_PID_2113_BSTCTRL1_REG	(0x60)
#define AW_PID_2113_BSTCTRL2_REG	(0x61)
#define AW_PID_2113_BSTCTRL3_REG	(0x62)
#define AW_PID_2113_BSTCTRL4_REG	(0x63)
#define AW_PID_2113_BSTCTRL5_REG	(0x64)
#define AW_PID_2113_BSTCTRL6_REG	(0x65)
#define AW_PID_2113_BSTCTRL7_REG	(0x66)
#define AW_PID_2113_BSTCTRL8_REG	(0x67)
#define AW_PID_2113_BSTCTRL9_REG	(0x68)
#define AW_PID_2113_TM_REG		(0x6F)
#define AW_PID_2113_TESTCTRL1_REG	(0x70)
#define AW_PID_2113_TESTCTRL2_REG	(0x71)
#define AW_PID_2113_EFCTRL1_REG		(0x72)
#define AW_PID_2113_EFCTRL2_REG		(0x73)
#define AW_PID_2113_EFWH_REG		(0x74)
#define AW_PID_2113_EFWM2_REG		(0x75)
#define AW_PID_2113_EFWM1_REG		(0x76)
#define AW_PID_2113_EFWL_REG		(0x77)
#define AW_PID_2113_EFRH4_REG		(0x78)
#define AW_PID_2113_EFRH3_REG		(0x79)
#define AW_PID_2113_EFRH2_REG		(0x7A)
#define AW_PID_2113_EFRH1_REG		(0x7B)
#define AW_PID_2113_EFRL4_REG		(0x7C)
#define AW_PID_2113_EFRL3_REG		(0x7D)
#define AW_PID_2113_EFRL2_REG		(0x7E)
#define AW_PID_2113_EFRL1_REG		(0x7F)

/********************************************
 * Register Access
 *******************************************/
#define AW_PID_2113_REG_MAX	(0x80)

#define AW_PID_2113_REG_NONE_ACCESS					(0)
#define AW_PID_2113_REG_RD_ACCESS					(1 << 0)
#define AW_PID_2113_REG_WR_ACCESS					(1 << 1)

const unsigned char aw_pid_2113_reg_access[AW_PID_2113_REG_MAX] = {
	[AW_PID_2113_ID_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_SYSST_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_SYSINT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_SYSINTM_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SYSCTRL_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SYSCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_I2SCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_I2SCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_I2SCTRL3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG4_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG5_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG6_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG7_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG8_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_PWMCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_PWMCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_I2SCFG1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DBGCTRL_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG9_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACCFG10_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DACST_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_VBAT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_TEMP_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_PVDD_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_ISNDAT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_VSNDAT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_I2SINT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_I2SCAPCNT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_ANASTA1_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_ANASTA2_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_ANASTA3_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_TESTDET_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_DSMCFG1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG4_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG5_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG6_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG7_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DSMCFG8_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_TESTIN_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_TESTOUT_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_SADCCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL4_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL5_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL6_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_SADCCTRL7_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_VSNTM1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_VSNTM2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_ISNCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_ISNCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_PLLCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_PLLCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_PLLCTRL3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_CDACTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_CDACTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DITHERCFG1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DITHERCFG2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_DITHERCFG3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_CPCTRL_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL3_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL4_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL5_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL6_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL7_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL8_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_BSTCTRL9_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_TM_REG]	= (AW_PID_2113_REG_NONE_ACCESS),
	[AW_PID_2113_TESTCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_TESTCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFCTRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFCTRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFWH_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFWM2_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFWM1_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFWL_REG]	= (AW_PID_2113_REG_RD_ACCESS | AW_PID_2113_REG_WR_ACCESS),
	[AW_PID_2113_EFRH4_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRH3_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRH2_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRH1_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRL4_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRL3_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRL2_REG]	= (AW_PID_2113_REG_RD_ACCESS),
	[AW_PID_2113_EFRL1_REG]	= (AW_PID_2113_REG_RD_ACCESS),
};

/* detail information of registers begin */
/* ID (0x00) detail */
/* IDCODE bit 15:0 (ID 0x00) */
#define AW_PID_2113_IDCODE_START_BIT	(0)
#define AW_PID_2113_IDCODE_BITS_LEN	(16)
#define AW_PID_2113_IDCODE_MASK	\
	(~(((1<<AW_PID_2113_IDCODE_BITS_LEN)-1) << AW_PID_2113_IDCODE_START_BIT))

#define AW_PID_2113_IDCODE_DEFAULT_VALUE	(0x2113)
#define AW_PID_2113_IDCODE_DEFAULT	\
	(AW_PID_2113_IDCODE_DEFAULT_VALUE << AW_PID_2113_IDCODE_START_BIT)

/* default value of ID (0x00) */
/* #define AW_PID_2113_ID_DEFAULT		(0x2113) */

/* SYSST (0x01) detail */
/* OVP2S bit 15 (SYSST 0x01) */
#define AW_PID_2113_OVP2S_START_BIT	(15)
#define AW_PID_2113_OVP2S_BITS_LEN	(1)
#define AW_PID_2113_OVP2S_MASK	\
	(~(((1<<AW_PID_2113_OVP2S_BITS_LEN)-1) << AW_PID_2113_OVP2S_START_BIT))

#define AW_PID_2113_OVP2S_NORMAL	(0)
#define AW_PID_2113_OVP2S_NORMAL_VALUE	\
	(AW_PID_2113_OVP2S_NORMAL << AW_PID_2113_OVP2S_START_BIT)

#define AW_PID_2113_OVP2S_OVP	(1)
#define AW_PID_2113_OVP2S_OVP_VALUE	\
	(AW_PID_2113_OVP2S_OVP << AW_PID_2113_OVP2S_START_BIT)

#define AW_PID_2113_OVP2S_DEFAULT_VALUE	(0)
#define AW_PID_2113_OVP2S_DEFAULT	\
	(AW_PID_2113_OVP2S_DEFAULT_VALUE << AW_PID_2113_OVP2S_START_BIT)

/* UVLS bit 14 (SYSST 0x01) */
#define AW_PID_2113_UVLS_START_BIT	(14)
#define AW_PID_2113_UVLS_BITS_LEN	(1)
#define AW_PID_2113_UVLS_MASK	\
	(~(((1<<AW_PID_2113_UVLS_BITS_LEN)-1) << AW_PID_2113_UVLS_START_BIT))

#define AW_PID_2113_UVLS_NORMAL	(0)
#define AW_PID_2113_UVLS_NORMAL_VALUE	\
	(AW_PID_2113_UVLS_NORMAL << AW_PID_2113_UVLS_START_BIT)

#define AW_PID_2113_UVLS_UVLO	(1)
#define AW_PID_2113_UVLS_UVLO_VALUE	\
	(AW_PID_2113_UVLS_UVLO << AW_PID_2113_UVLS_START_BIT)

#define AW_PID_2113_UVLS_DEFAULT_VALUE	(0)
#define AW_PID_2113_UVLS_DEFAULT	\
	(AW_PID_2113_UVLS_DEFAULT_VALUE << AW_PID_2113_UVLS_START_BIT)

/* ADPS bit 13 (SYSST 0x01) */
#define AW_PID_2113_ADPS_START_BIT	(13)
#define AW_PID_2113_ADPS_BITS_LEN	(1)
#define AW_PID_2113_ADPS_MASK	\
	(~(((1<<AW_PID_2113_ADPS_BITS_LEN)-1) << AW_PID_2113_ADPS_START_BIT))

#define AW_PID_2113_ADPS_TRANSPARENT	(0)
#define AW_PID_2113_ADPS_TRANSPARENT_VALUE	\
	(AW_PID_2113_ADPS_TRANSPARENT << AW_PID_2113_ADPS_START_BIT)

#define AW_PID_2113_ADPS_BOOST	(1)
#define AW_PID_2113_ADPS_BOOST_VALUE	\
	(AW_PID_2113_ADPS_BOOST << AW_PID_2113_ADPS_START_BIT)

#define AW_PID_2113_ADPS_DEFAULT_VALUE	(0)
#define AW_PID_2113_ADPS_DEFAULT	\
	(AW_PID_2113_ADPS_DEFAULT_VALUE << AW_PID_2113_ADPS_START_BIT)

/* DSPS bit 12 (SYSST 0x01) */
#define AW_PID_2113_DSPS_START_BIT	(12)
#define AW_PID_2113_DSPS_BITS_LEN	(1)
#define AW_PID_2113_DSPS_MASK	\
	(~(((1<<AW_PID_2113_DSPS_BITS_LEN)-1) << AW_PID_2113_DSPS_START_BIT))

#define AW_PID_2113_DSPS_NORMAL	(0)
#define AW_PID_2113_DSPS_NORMAL_VALUE	\
	(AW_PID_2113_DSPS_NORMAL << AW_PID_2113_DSPS_START_BIT)

#define AW_PID_2113_DSPS_DSP_STABLE	(1)
#define AW_PID_2113_DSPS_DSP_STABLE_VALUE	\
	(AW_PID_2113_DSPS_DSP_STABLE << AW_PID_2113_DSPS_START_BIT)

#define AW_PID_2113_DSPS_DEFAULT_VALUE	(0)
#define AW_PID_2113_DSPS_DEFAULT	\
	(AW_PID_2113_DSPS_DEFAULT_VALUE << AW_PID_2113_DSPS_START_BIT)

/* BSTOCS bit 11 (SYSST 0x01) */
#define AW_PID_2113_BSTOCS_START_BIT	(11)
#define AW_PID_2113_BSTOCS_BITS_LEN	(1)
#define AW_PID_2113_BSTOCS_MASK	\
	(~(((1<<AW_PID_2113_BSTOCS_BITS_LEN)-1) << AW_PID_2113_BSTOCS_START_BIT))

#define AW_PID_2113_BSTOCS_NORMAL	(0)
#define AW_PID_2113_BSTOCS_NORMAL_VALUE	\
	(AW_PID_2113_BSTOCS_NORMAL << AW_PID_2113_BSTOCS_START_BIT)

#define AW_PID_2113_BSTOCS_OVER_CURRENT	(1)
#define AW_PID_2113_BSTOCS_OVER_CURRENT_VALUE	\
	(AW_PID_2113_BSTOCS_OVER_CURRENT << AW_PID_2113_BSTOCS_START_BIT)

#define AW_PID_2113_BSTOCS_DEFAULT_VALUE	(0)
#define AW_PID_2113_BSTOCS_DEFAULT	\
	(AW_PID_2113_BSTOCS_DEFAULT_VALUE << AW_PID_2113_BSTOCS_START_BIT)

/* OVPS bit 10 (SYSST 0x01) */
#define AW_PID_2113_OVPS_START_BIT	(10)
#define AW_PID_2113_OVPS_BITS_LEN	(1)
#define AW_PID_2113_OVPS_MASK	\
	(~(((1<<AW_PID_2113_OVPS_BITS_LEN)-1) << AW_PID_2113_OVPS_START_BIT))

#define AW_PID_2113_OVPS_NORMAL	(0)
#define AW_PID_2113_OVPS_NORMAL_VALUE	\
	(AW_PID_2113_OVPS_NORMAL << AW_PID_2113_OVPS_START_BIT)

#define AW_PID_2113_OVPS_OVP	(1)
#define AW_PID_2113_OVPS_OVP_VALUE	\
	(AW_PID_2113_OVPS_OVP << AW_PID_2113_OVPS_START_BIT)

#define AW_PID_2113_OVPS_DEFAULT_VALUE	(0)
#define AW_PID_2113_OVPS_DEFAULT	\
	(AW_PID_2113_OVPS_DEFAULT_VALUE << AW_PID_2113_OVPS_START_BIT)

/* BSTS bit 9 (SYSST 0x01) */
#define AW_PID_2113_BSTS_START_BIT	(9)
#define AW_PID_2113_BSTS_BITS_LEN	(1)
#define AW_PID_2113_BSTS_MASK	\
	(~(((1<<AW_PID_2113_BSTS_BITS_LEN)-1) << AW_PID_2113_BSTS_START_BIT))

#define AW_PID_2113_BSTS_NOT_FINISHED	(0)
#define AW_PID_2113_BSTS_NOT_FINISHED_VALUE	\
	(AW_PID_2113_BSTS_NOT_FINISHED << AW_PID_2113_BSTS_START_BIT)

#define AW_PID_2113_BSTS_FINISHED	(1)
#define AW_PID_2113_BSTS_FINISHED_VALUE	\
	(AW_PID_2113_BSTS_FINISHED << AW_PID_2113_BSTS_START_BIT)

#define AW_PID_2113_BSTS_DEFAULT_VALUE	(0)
#define AW_PID_2113_BSTS_DEFAULT	\
	(AW_PID_2113_BSTS_DEFAULT_VALUE << AW_PID_2113_BSTS_START_BIT)

/* SWS bit 8 (SYSST 0x01) */
#define AW_PID_2113_SWS_START_BIT	(8)
#define AW_PID_2113_SWS_BITS_LEN	(1)
#define AW_PID_2113_SWS_MASK	\
	(~(((1<<AW_PID_2113_SWS_BITS_LEN)-1) << AW_PID_2113_SWS_START_BIT))

#define AW_PID_2113_SWS_NOT_SWITCHING	(0)
#define AW_PID_2113_SWS_NOT_SWITCHING_VALUE	\
	(AW_PID_2113_SWS_NOT_SWITCHING << AW_PID_2113_SWS_START_BIT)

#define AW_PID_2113_SWS_SWITCHING	(1)
#define AW_PID_2113_SWS_SWITCHING_VALUE	\
	(AW_PID_2113_SWS_SWITCHING << AW_PID_2113_SWS_START_BIT)

#define AW_PID_2113_SWS_DEFAULT_VALUE	(0)
#define AW_PID_2113_SWS_DEFAULT	\
	(AW_PID_2113_SWS_DEFAULT_VALUE << AW_PID_2113_SWS_START_BIT)

/* CLIPS bit 7 (SYSST 0x01) */
#define AW_PID_2113_CLIPS_START_BIT	(7)
#define AW_PID_2113_CLIPS_BITS_LEN	(1)
#define AW_PID_2113_CLIPS_MASK	\
	(~(((1<<AW_PID_2113_CLIPS_BITS_LEN)-1) << AW_PID_2113_CLIPS_START_BIT))

#define AW_PID_2113_CLIPS_NOT_CLIPPING	(0)
#define AW_PID_2113_CLIPS_NOT_CLIPPING_VALUE	\
	(AW_PID_2113_CLIPS_NOT_CLIPPING << AW_PID_2113_CLIPS_START_BIT)

#define AW_PID_2113_CLIPS_CLIPPING	(1)
#define AW_PID_2113_CLIPS_CLIPPING_VALUE	\
	(AW_PID_2113_CLIPS_CLIPPING << AW_PID_2113_CLIPS_START_BIT)

#define AW_PID_2113_CLIPS_DEFAULT_VALUE	(0)
#define AW_PID_2113_CLIPS_DEFAULT	\
	(AW_PID_2113_CLIPS_DEFAULT_VALUE << AW_PID_2113_CLIPS_START_BIT)

/* WDS bit 6 (SYSST 0x01) */
#define AW_PID_2113_WDS_START_BIT	(6)
#define AW_PID_2113_WDS_BITS_LEN	(1)
#define AW_PID_2113_WDS_MASK	\
	(~(((1<<AW_PID_2113_WDS_BITS_LEN)-1) << AW_PID_2113_WDS_START_BIT))

#define AW_PID_2113_WDS_NORMAL	(0)
#define AW_PID_2113_WDS_NORMAL_VALUE	\
	(AW_PID_2113_WDS_NORMAL << AW_PID_2113_WDS_START_BIT)

#define AW_PID_2113_WDS_ABNORMAL	(1)
#define AW_PID_2113_WDS_ABNORMAL_VALUE	\
	(AW_PID_2113_WDS_ABNORMAL << AW_PID_2113_WDS_START_BIT)

#define AW_PID_2113_WDS_DEFAULT_VALUE	(0)
#define AW_PID_2113_WDS_DEFAULT	\
	(AW_PID_2113_WDS_DEFAULT_VALUE << AW_PID_2113_WDS_START_BIT)

/* NOCLKS bit 5 (SYSST 0x01) */
#define AW_PID_2113_NOCLKS_START_BIT	(5)
#define AW_PID_2113_NOCLKS_BITS_LEN	(1)
#define AW_PID_2113_NOCLKS_MASK	\
	(~(((1<<AW_PID_2113_NOCLKS_BITS_LEN)-1) << AW_PID_2113_NOCLKS_START_BIT))

#define AW_PID_2113_NOCLKS_CLOCK_OK	(0)
#define AW_PID_2113_NOCLKS_CLOCK_OK_VALUE	\
	(AW_PID_2113_NOCLKS_CLOCK_OK << AW_PID_2113_NOCLKS_START_BIT)

#define AW_PID_2113_NOCLKS_NO_CLOCK	(1)
#define AW_PID_2113_NOCLKS_NO_CLOCK_VALUE	\
	(AW_PID_2113_NOCLKS_NO_CLOCK << AW_PID_2113_NOCLKS_START_BIT)

#define AW_PID_2113_NOCLKS_DEFAULT_VALUE	(0)
#define AW_PID_2113_NOCLKS_DEFAULT	\
	(AW_PID_2113_NOCLKS_DEFAULT_VALUE << AW_PID_2113_NOCLKS_START_BIT)

/* CLKS bit 4 (SYSST 0x01) */
#define AW_PID_2113_CLKS_START_BIT	(4)
#define AW_PID_2113_CLKS_BITS_LEN	(1)
#define AW_PID_2113_CLKS_MASK	\
	(~(((1<<AW_PID_2113_CLKS_BITS_LEN)-1) << AW_PID_2113_CLKS_START_BIT))

#define AW_PID_2113_CLKS_NOT_STABLE	(0)
#define AW_PID_2113_CLKS_NOT_STABLE_VALUE	\
	(AW_PID_2113_CLKS_NOT_STABLE << AW_PID_2113_CLKS_START_BIT)

#define AW_PID_2113_CLKS_STABLE	(1)
#define AW_PID_2113_CLKS_STABLE_VALUE	\
	(AW_PID_2113_CLKS_STABLE << AW_PID_2113_CLKS_START_BIT)

#define AW_PID_2113_CLKS_DEFAULT_VALUE	(0)
#define AW_PID_2113_CLKS_DEFAULT	\
	(AW_PID_2113_CLKS_DEFAULT_VALUE << AW_PID_2113_CLKS_START_BIT)

/* OCDS bit 3 (SYSST 0x01) */
#define AW_PID_2113_OCDS_START_BIT	(3)
#define AW_PID_2113_OCDS_BITS_LEN	(1)
#define AW_PID_2113_OCDS_MASK	\
	(~(((1<<AW_PID_2113_OCDS_BITS_LEN)-1) << AW_PID_2113_OCDS_START_BIT))

#define AW_PID_2113_OCDS_NORAML	(0)
#define AW_PID_2113_OCDS_NORAML_VALUE	\
	(AW_PID_2113_OCDS_NORAML << AW_PID_2113_OCDS_START_BIT)

#define AW_PID_2113_OCDS_OC	(1)
#define AW_PID_2113_OCDS_OC_VALUE	\
	(AW_PID_2113_OCDS_OC << AW_PID_2113_OCDS_START_BIT)

#define AW_PID_2113_OCDS_DEFAULT_VALUE	(0)
#define AW_PID_2113_OCDS_DEFAULT	\
	(AW_PID_2113_OCDS_DEFAULT_VALUE << AW_PID_2113_OCDS_START_BIT)

/* BOPS bit 2 (SYSST 0x01) */
#define AW_PID_2113_BOPS_START_BIT	(2)
#define AW_PID_2113_BOPS_BITS_LEN	(1)
#define AW_PID_2113_BOPS_MASK	\
	(~(((1<<AW_PID_2113_BOPS_BITS_LEN)-1) << AW_PID_2113_BOPS_START_BIT))

#define AW_PID_2113_BOPS_NOT_TRIGGERED	(0)
#define AW_PID_2113_BOPS_NOT_TRIGGERED_VALUE	\
	(AW_PID_2113_BOPS_NOT_TRIGGERED << AW_PID_2113_BOPS_START_BIT)

#define AW_PID_2113_BOPS_TRIGGERED	(1)
#define AW_PID_2113_BOPS_TRIGGERED_VALUE	\
	(AW_PID_2113_BOPS_TRIGGERED << AW_PID_2113_BOPS_START_BIT)

#define AW_PID_2113_BOPS_DEFAULT_VALUE	(0)
#define AW_PID_2113_BOPS_DEFAULT	\
	(AW_PID_2113_BOPS_DEFAULT_VALUE << AW_PID_2113_BOPS_START_BIT)

/* OTHS bit 1 (SYSST 0x01) */
#define AW_PID_2113_OTHS_START_BIT	(1)
#define AW_PID_2113_OTHS_BITS_LEN	(1)
#define AW_PID_2113_OTHS_MASK	\
	(~(((1<<AW_PID_2113_OTHS_BITS_LEN)-1) << AW_PID_2113_OTHS_START_BIT))

#define AW_PID_2113_OTHS_NORMAL	(0)
#define AW_PID_2113_OTHS_NORMAL_VALUE	\
	(AW_PID_2113_OTHS_NORMAL << AW_PID_2113_OTHS_START_BIT)

#define AW_PID_2113_OTHS_OT	(1)
#define AW_PID_2113_OTHS_OT_VALUE	\
	(AW_PID_2113_OTHS_OT << AW_PID_2113_OTHS_START_BIT)

#define AW_PID_2113_OTHS_DEFAULT_VALUE	(0)
#define AW_PID_2113_OTHS_DEFAULT	\
	(AW_PID_2113_OTHS_DEFAULT_VALUE << AW_PID_2113_OTHS_START_BIT)

/* PLLS bit 0 (SYSST 0x01) */
#define AW_PID_2113_PLLS_START_BIT	(0)
#define AW_PID_2113_PLLS_BITS_LEN	(1)
#define AW_PID_2113_PLLS_MASK	\
	(~(((1<<AW_PID_2113_PLLS_BITS_LEN)-1) << AW_PID_2113_PLLS_START_BIT))

#define AW_PID_2113_PLLS_UNLOCKED	(0)
#define AW_PID_2113_PLLS_UNLOCKED_VALUE	\
	(AW_PID_2113_PLLS_UNLOCKED << AW_PID_2113_PLLS_START_BIT)

#define AW_PID_2113_PLLS_LOCKED	(1)
#define AW_PID_2113_PLLS_LOCKED_VALUE	\
	(AW_PID_2113_PLLS_LOCKED << AW_PID_2113_PLLS_START_BIT)

#define AW_PID_2113_PLLS_DEFAULT_VALUE	(0)
#define AW_PID_2113_PLLS_DEFAULT	\
	(AW_PID_2113_PLLS_DEFAULT_VALUE << AW_PID_2113_PLLS_START_BIT)

/* default value of SYSST (0x01) */
/* #define AW_PID_2113_SYSST_DEFAULT		(0x0000) */

#define AW_PID_2113_SYSST_CHECK_MASK \
	(~(AW_PID_2113_UVLS_UVLO_VALUE | \
	AW_PID_2113_BSTOCS_OVER_CURRENT_VALUE | \
	AW_PID_2113_BSTS_FINISHED_VALUE | \
	AW_PID_2113_SWS_SWITCHING_VALUE | \
	AW_PID_2113_NOCLKS_NO_CLOCK_VALUE | \
	AW_PID_2113_CLKS_STABLE_VALUE | \
	AW_PID_2113_OCDS_OC_VALUE | \
	AW_PID_2113_OTHS_OT_VALUE | \
	AW_PID_2113_PLLS_LOCKED_VALUE))

#define AW_PID_2113_SYSST_CHECK \
	(AW_PID_2113_BSTS_FINISHED_VALUE | \
	AW_PID_2113_SWS_SWITCHING_VALUE | \
	AW_PID_2113_CLKS_STABLE_VALUE | \
	AW_PID_2113_PLLS_LOCKED_VALUE)

#define AW_PID_2113_IIS_CHECK \
	(AW_PID_2113_CLKS_STABLE_VALUE | \
	AW_PID_2113_PLLS_LOCKED_VALUE)

/* SYSINT (0x02) detail */
/* OVP2I bit 15 (SYSINT 0x02) */
#define AW_PID_2113_OVP2I_START_BIT	(15)
#define AW_PID_2113_OVP2I_BITS_LEN	(1)
#define AW_PID_2113_OVP2I_MASK	\
	(~(((1<<AW_PID_2113_OVP2I_BITS_LEN)-1) << AW_PID_2113_OVP2I_START_BIT))

#define AW_PID_2113_OVP2I_DEFAULT_VALUE	(0)
#define AW_PID_2113_OVP2I_DEFAULT	\
	(AW_PID_2113_OVP2I_DEFAULT_VALUE << AW_PID_2113_OVP2I_START_BIT)

/* UVLI bit 14 (SYSINT 0x02) */
#define AW_PID_2113_UVLI_START_BIT	(14)
#define AW_PID_2113_UVLI_BITS_LEN	(1)
#define AW_PID_2113_UVLI_MASK	\
	(~(((1<<AW_PID_2113_UVLI_BITS_LEN)-1) << AW_PID_2113_UVLI_START_BIT))

#define AW_PID_2113_UVLI_DEFAULT_VALUE	(0)
#define AW_PID_2113_UVLI_DEFAULT	\
	(AW_PID_2113_UVLI_DEFAULT_VALUE << AW_PID_2113_UVLI_START_BIT)

/* ADPI bit 13 (SYSINT 0x02) */
#define AW_PID_2113_ADPI_START_BIT	(13)
#define AW_PID_2113_ADPI_BITS_LEN	(1)
#define AW_PID_2113_ADPI_MASK	\
	(~(((1<<AW_PID_2113_ADPI_BITS_LEN)-1) << AW_PID_2113_ADPI_START_BIT))

#define AW_PID_2113_ADPI_DEFAULT_VALUE	(0)
#define AW_PID_2113_ADPI_DEFAULT	\
	(AW_PID_2113_ADPI_DEFAULT_VALUE << AW_PID_2113_ADPI_START_BIT)

/* DSPI bit 12 (SYSINT 0x02) */
#define AW_PID_2113_DSPI_START_BIT	(12)
#define AW_PID_2113_DSPI_BITS_LEN	(1)
#define AW_PID_2113_DSPI_MASK	\
	(~(((1<<AW_PID_2113_DSPI_BITS_LEN)-1) << AW_PID_2113_DSPI_START_BIT))

#define AW_PID_2113_DSPI_DEFAULT_VALUE	(0)
#define AW_PID_2113_DSPI_DEFAULT	\
	(AW_PID_2113_DSPI_DEFAULT_VALUE << AW_PID_2113_DSPI_START_BIT)

/* BSTOCI bit 11 (SYSINT 0x02) */
#define AW_PID_2113_BSTOCI_START_BIT	(11)
#define AW_PID_2113_BSTOCI_BITS_LEN	(1)
#define AW_PID_2113_BSTOCI_MASK	\
	(~(((1<<AW_PID_2113_BSTOCI_BITS_LEN)-1) << AW_PID_2113_BSTOCI_START_BIT))

#define AW_PID_2113_BSTOCI_DEFAULT_VALUE	(0)
#define AW_PID_2113_BSTOCI_DEFAULT	\
	(AW_PID_2113_BSTOCI_DEFAULT_VALUE << AW_PID_2113_BSTOCI_START_BIT)

/* OVPI bit 10 (SYSINT 0x02) */
#define AW_PID_2113_OVPI_START_BIT	(10)
#define AW_PID_2113_OVPI_BITS_LEN	(1)
#define AW_PID_2113_OVPI_MASK	\
	(~(((1<<AW_PID_2113_OVPI_BITS_LEN)-1) << AW_PID_2113_OVPI_START_BIT))

#define AW_PID_2113_OVPI_DEFAULT_VALUE	(0)
#define AW_PID_2113_OVPI_DEFAULT	\
	(AW_PID_2113_OVPI_DEFAULT_VALUE << AW_PID_2113_OVPI_START_BIT)

/* BSTI bit 9 (SYSINT 0x02) */
#define AW_PID_2113_BSTI_START_BIT	(9)
#define AW_PID_2113_BSTI_BITS_LEN	(1)
#define AW_PID_2113_BSTI_MASK	\
	(~(((1<<AW_PID_2113_BSTI_BITS_LEN)-1) << AW_PID_2113_BSTI_START_BIT))

#define AW_PID_2113_BSTI_DEFAULT_VALUE	(0)
#define AW_PID_2113_BSTI_DEFAULT	\
	(AW_PID_2113_BSTI_DEFAULT_VALUE << AW_PID_2113_BSTI_START_BIT)

/* SWI bit 8 (SYSINT 0x02) */
#define AW_PID_2113_SWI_START_BIT	(8)
#define AW_PID_2113_SWI_BITS_LEN	(1)
#define AW_PID_2113_SWI_MASK	\
	(~(((1<<AW_PID_2113_SWI_BITS_LEN)-1) << AW_PID_2113_SWI_START_BIT))

#define AW_PID_2113_SWI_DEFAULT_VALUE	(0)
#define AW_PID_2113_SWI_DEFAULT	\
	(AW_PID_2113_SWI_DEFAULT_VALUE << AW_PID_2113_SWI_START_BIT)

/* CLIPI bit 7 (SYSINT 0x02) */
#define AW_PID_2113_CLIPI_START_BIT	(7)
#define AW_PID_2113_CLIPI_BITS_LEN	(1)
#define AW_PID_2113_CLIPI_MASK	\
	(~(((1<<AW_PID_2113_CLIPI_BITS_LEN)-1) << AW_PID_2113_CLIPI_START_BIT))

#define AW_PID_2113_CLIPI_DEFAULT_VALUE	(0)
#define AW_PID_2113_CLIPI_DEFAULT	\
	(AW_PID_2113_CLIPI_DEFAULT_VALUE << AW_PID_2113_CLIPI_START_BIT)

/* WDI bit 6 (SYSINT 0x02) */
#define AW_PID_2113_WDI_START_BIT	(6)
#define AW_PID_2113_WDI_BITS_LEN	(1)
#define AW_PID_2113_WDI_MASK	\
	(~(((1<<AW_PID_2113_WDI_BITS_LEN)-1) << AW_PID_2113_WDI_START_BIT))

#define AW_PID_2113_WDI_DEFAULT_VALUE	(0)
#define AW_PID_2113_WDI_DEFAULT	\
	(AW_PID_2113_WDI_DEFAULT_VALUE << AW_PID_2113_WDI_START_BIT)

/* NOCLKI bit 5 (SYSINT 0x02) */
#define AW_PID_2113_NOCLKI_START_BIT	(5)
#define AW_PID_2113_NOCLKI_BITS_LEN	(1)
#define AW_PID_2113_NOCLKI_MASK	\
	(~(((1<<AW_PID_2113_NOCLKI_BITS_LEN)-1) << AW_PID_2113_NOCLKI_START_BIT))

#define AW_PID_2113_NOCLKI_DEFAULT_VALUE	(0)
#define AW_PID_2113_NOCLKI_DEFAULT	\
	(AW_PID_2113_NOCLKI_DEFAULT_VALUE << AW_PID_2113_NOCLKI_START_BIT)

/* CLKI bit 4 (SYSINT 0x02) */
#define AW_PID_2113_CLKI_START_BIT	(4)
#define AW_PID_2113_CLKI_BITS_LEN	(1)
#define AW_PID_2113_CLKI_MASK	\
	(~(((1<<AW_PID_2113_CLKI_BITS_LEN)-1) << AW_PID_2113_CLKI_START_BIT))

#define AW_PID_2113_CLKI_DEFAULT_VALUE	(0)
#define AW_PID_2113_CLKI_DEFAULT	\
	(AW_PID_2113_CLKI_DEFAULT_VALUE << AW_PID_2113_CLKI_START_BIT)

/* OCDI bit 3 (SYSINT 0x02) */
#define AW_PID_2113_OCDI_START_BIT	(3)
#define AW_PID_2113_OCDI_BITS_LEN	(1)
#define AW_PID_2113_OCDI_MASK	\
	(~(((1<<AW_PID_2113_OCDI_BITS_LEN)-1) << AW_PID_2113_OCDI_START_BIT))

#define AW_PID_2113_OCDI_DEFAULT_VALUE	(0)
#define AW_PID_2113_OCDI_DEFAULT	\
	(AW_PID_2113_OCDI_DEFAULT_VALUE << AW_PID_2113_OCDI_START_BIT)

/* BOPI bit 2 (SYSINT 0x02) */
#define AW_PID_2113_BOPI_START_BIT	(2)
#define AW_PID_2113_BOPI_BITS_LEN	(1)
#define AW_PID_2113_BOPI_MASK	\
	(~(((1<<AW_PID_2113_BOPI_BITS_LEN)-1) << AW_PID_2113_BOPI_START_BIT))

#define AW_PID_2113_BOPI_DEFAULT_VALUE	(0)
#define AW_PID_2113_BOPI_DEFAULT	\
	(AW_PID_2113_BOPI_DEFAULT_VALUE << AW_PID_2113_BOPI_START_BIT)

/* OTHI bit 1 (SYSINT 0x02) */
#define AW_PID_2113_OTHI_START_BIT	(1)
#define AW_PID_2113_OTHI_BITS_LEN	(1)
#define AW_PID_2113_OTHI_MASK	\
	(~(((1<<AW_PID_2113_OTHI_BITS_LEN)-1) << AW_PID_2113_OTHI_START_BIT))

#define AW_PID_2113_OTHI_DEFAULT_VALUE	(0)
#define AW_PID_2113_OTHI_DEFAULT	\
	(AW_PID_2113_OTHI_DEFAULT_VALUE << AW_PID_2113_OTHI_START_BIT)

/* PLLI bit 0 (SYSINT 0x02) */
#define AW_PID_2113_PLLI_START_BIT	(0)
#define AW_PID_2113_PLLI_BITS_LEN	(1)
#define AW_PID_2113_PLLI_MASK	\
	(~(((1<<AW_PID_2113_PLLI_BITS_LEN)-1) << AW_PID_2113_PLLI_START_BIT))

#define AW_PID_2113_PLLI_DEFAULT_VALUE	(0)
#define AW_PID_2113_PLLI_DEFAULT	\
	(AW_PID_2113_PLLI_DEFAULT_VALUE << AW_PID_2113_PLLI_START_BIT)

/* default value of SYSINT (0x02) */
/* #define AW_PID_2113_SYSINT_DEFAULT		(0x0000) */

/* SYSINTM (0x03) detail */
/* OVP2M bit 15 (SYSINTM 0x03) */
#define AW_PID_2113_OVP2M_START_BIT	(15)
#define AW_PID_2113_OVP2M_BITS_LEN	(1)
#define AW_PID_2113_OVP2M_MASK	\
	(~(((1<<AW_PID_2113_OVP2M_BITS_LEN)-1) << AW_PID_2113_OVP2M_START_BIT))

#define AW_PID_2113_OVP2M_DEFAULT_VALUE	(1)
#define AW_PID_2113_OVP2M_DEFAULT	\
	(AW_PID_2113_OVP2M_DEFAULT_VALUE << AW_PID_2113_OVP2M_START_BIT)

/* UVLM bit 14 (SYSINTM 0x03) */
#define AW_PID_2113_UVLM_START_BIT	(14)
#define AW_PID_2113_UVLM_BITS_LEN	(1)
#define AW_PID_2113_UVLM_MASK	\
	(~(((1<<AW_PID_2113_UVLM_BITS_LEN)-1) << AW_PID_2113_UVLM_START_BIT))

#define AW_PID_2113_UVLM_DEFAULT_VALUE	(1)
#define AW_PID_2113_UVLM_DEFAULT	\
	(AW_PID_2113_UVLM_DEFAULT_VALUE << AW_PID_2113_UVLM_START_BIT)

/* ADPM bit 13 (SYSINTM 0x03) */
#define AW_PID_2113_ADPM_START_BIT	(13)
#define AW_PID_2113_ADPM_BITS_LEN	(1)
#define AW_PID_2113_ADPM_MASK	\
	(~(((1<<AW_PID_2113_ADPM_BITS_LEN)-1) << AW_PID_2113_ADPM_START_BIT))

#define AW_PID_2113_ADPM_DEFAULT_VALUE	(1)
#define AW_PID_2113_ADPM_DEFAULT	\
	(AW_PID_2113_ADPM_DEFAULT_VALUE << AW_PID_2113_ADPM_START_BIT)

/* DSPM bit 12 (SYSINTM 0x03) */
#define AW_PID_2113_DSPM_START_BIT	(12)
#define AW_PID_2113_DSPM_BITS_LEN	(1)
#define AW_PID_2113_DSPM_MASK	\
	(~(((1<<AW_PID_2113_DSPM_BITS_LEN)-1) << AW_PID_2113_DSPM_START_BIT))

#define AW_PID_2113_DSPM_DEFAULT_VALUE	(1)
#define AW_PID_2113_DSPM_DEFAULT	\
	(AW_PID_2113_DSPM_DEFAULT_VALUE << AW_PID_2113_DSPM_START_BIT)

/* BSTOCM bit 11 (SYSINTM 0x03) */
#define AW_PID_2113_BSTOCM_START_BIT	(11)
#define AW_PID_2113_BSTOCM_BITS_LEN	(1)
#define AW_PID_2113_BSTOCM_MASK	\
	(~(((1<<AW_PID_2113_BSTOCM_BITS_LEN)-1) << AW_PID_2113_BSTOCM_START_BIT))

#define AW_PID_2113_BSTOCM_DEFAULT_VALUE	(1)
#define AW_PID_2113_BSTOCM_DEFAULT	\
	(AW_PID_2113_BSTOCM_DEFAULT_VALUE << AW_PID_2113_BSTOCM_START_BIT)

/* OVPM bit 10 (SYSINTM 0x03) */
#define AW_PID_2113_OVPM_START_BIT	(10)
#define AW_PID_2113_OVPM_BITS_LEN	(1)
#define AW_PID_2113_OVPM_MASK	\
	(~(((1<<AW_PID_2113_OVPM_BITS_LEN)-1) << AW_PID_2113_OVPM_START_BIT))

#define AW_PID_2113_OVPM_DEFAULT_VALUE	(1)
#define AW_PID_2113_OVPM_DEFAULT	\
	(AW_PID_2113_OVPM_DEFAULT_VALUE << AW_PID_2113_OVPM_START_BIT)

/* BSTM bit 9 (SYSINTM 0x03) */
#define AW_PID_2113_BSTM_START_BIT	(9)
#define AW_PID_2113_BSTM_BITS_LEN	(1)
#define AW_PID_2113_BSTM_MASK	\
	(~(((1<<AW_PID_2113_BSTM_BITS_LEN)-1) << AW_PID_2113_BSTM_START_BIT))

#define AW_PID_2113_BSTM_DEFAULT_VALUE	(1)
#define AW_PID_2113_BSTM_DEFAULT	\
	(AW_PID_2113_BSTM_DEFAULT_VALUE << AW_PID_2113_BSTM_START_BIT)

/* SWM bit 8 (SYSINTM 0x03) */
#define AW_PID_2113_SWM_START_BIT	(8)
#define AW_PID_2113_SWM_BITS_LEN	(1)
#define AW_PID_2113_SWM_MASK	\
	(~(((1<<AW_PID_2113_SWM_BITS_LEN)-1) << AW_PID_2113_SWM_START_BIT))

#define AW_PID_2113_SWM_DEFAULT_VALUE	(1)
#define AW_PID_2113_SWM_DEFAULT	\
	(AW_PID_2113_SWM_DEFAULT_VALUE << AW_PID_2113_SWM_START_BIT)

/* CLIPM bit 7 (SYSINTM 0x03) */
#define AW_PID_2113_CLIPM_START_BIT	(7)
#define AW_PID_2113_CLIPM_BITS_LEN	(1)
#define AW_PID_2113_CLIPM_MASK	\
	(~(((1<<AW_PID_2113_CLIPM_BITS_LEN)-1) << AW_PID_2113_CLIPM_START_BIT))

#define AW_PID_2113_CLIPM_DEFAULT_VALUE	(1)
#define AW_PID_2113_CLIPM_DEFAULT	\
	(AW_PID_2113_CLIPM_DEFAULT_VALUE << AW_PID_2113_CLIPM_START_BIT)

/* WDM bit 6 (SYSINTM 0x03) */
#define AW_PID_2113_WDM_START_BIT	(6)
#define AW_PID_2113_WDM_BITS_LEN	(1)
#define AW_PID_2113_WDM_MASK	\
	(~(((1<<AW_PID_2113_WDM_BITS_LEN)-1) << AW_PID_2113_WDM_START_BIT))

#define AW_PID_2113_WDM_DEFAULT_VALUE	(1)
#define AW_PID_2113_WDM_DEFAULT	\
	(AW_PID_2113_WDM_DEFAULT_VALUE << AW_PID_2113_WDM_START_BIT)

/* NOCLKM bit 5 (SYSINTM 0x03) */
#define AW_PID_2113_NOCLKM_START_BIT	(5)
#define AW_PID_2113_NOCLKM_BITS_LEN	(1)
#define AW_PID_2113_NOCLKM_MASK	\
	(~(((1<<AW_PID_2113_NOCLKM_BITS_LEN)-1) << AW_PID_2113_NOCLKM_START_BIT))

#define AW_PID_2113_NOCLKM_DEFAULT_VALUE	(1)
#define AW_PID_2113_NOCLKM_DEFAULT	\
	(AW_PID_2113_NOCLKM_DEFAULT_VALUE << AW_PID_2113_NOCLKM_START_BIT)

/* CLKM bit 4 (SYSINTM 0x03) */
#define AW_PID_2113_CLKM_START_BIT	(4)
#define AW_PID_2113_CLKM_BITS_LEN	(1)
#define AW_PID_2113_CLKM_MASK	\
	(~(((1<<AW_PID_2113_CLKM_BITS_LEN)-1) << AW_PID_2113_CLKM_START_BIT))

#define AW_PID_2113_CLKM_DEFAULT_VALUE	(1)
#define AW_PID_2113_CLKM_DEFAULT	\
	(AW_PID_2113_CLKM_DEFAULT_VALUE << AW_PID_2113_CLKM_START_BIT)

/* OCDM bit 3 (SYSINTM 0x03) */
#define AW_PID_2113_OCDM_START_BIT	(3)
#define AW_PID_2113_OCDM_BITS_LEN	(1)
#define AW_PID_2113_OCDM_MASK	\
	(~(((1<<AW_PID_2113_OCDM_BITS_LEN)-1) << AW_PID_2113_OCDM_START_BIT))

#define AW_PID_2113_OCDM_DEFAULT_VALUE	(1)
#define AW_PID_2113_OCDM_DEFAULT	\
	(AW_PID_2113_OCDM_DEFAULT_VALUE << AW_PID_2113_OCDM_START_BIT)

/* BOPM bit 2 (SYSINTM 0x03) */
#define AW_PID_2113_BOPM_START_BIT	(2)
#define AW_PID_2113_BOPM_BITS_LEN	(1)
#define AW_PID_2113_BOPM_MASK	\
	(~(((1<<AW_PID_2113_BOPM_BITS_LEN)-1) << AW_PID_2113_BOPM_START_BIT))

#define AW_PID_2113_BOPM_DEFAULT_VALUE	(1)
#define AW_PID_2113_BOPM_DEFAULT	\
	(AW_PID_2113_BOPM_DEFAULT_VALUE << AW_PID_2113_BOPM_START_BIT)

/* OTHM bit 1 (SYSINTM 0x03) */
#define AW_PID_2113_OTHM_START_BIT	(1)
#define AW_PID_2113_OTHM_BITS_LEN	(1)
#define AW_PID_2113_OTHM_MASK	\
	(~(((1<<AW_PID_2113_OTHM_BITS_LEN)-1) << AW_PID_2113_OTHM_START_BIT))

#define AW_PID_2113_OTHM_DEFAULT_VALUE	(1)
#define AW_PID_2113_OTHM_DEFAULT	\
	(AW_PID_2113_OTHM_DEFAULT_VALUE << AW_PID_2113_OTHM_START_BIT)

/* PLLM bit 0 (SYSINTM 0x03) */
#define AW_PID_2113_PLLM_START_BIT	(0)
#define AW_PID_2113_PLLM_BITS_LEN	(1)
#define AW_PID_2113_PLLM_MASK	\
	(~(((1<<AW_PID_2113_PLLM_BITS_LEN)-1) << AW_PID_2113_PLLM_START_BIT))

#define AW_PID_2113_PLLM_DEFAULT_VALUE	(1)
#define AW_PID_2113_PLLM_DEFAULT	\
	(AW_PID_2113_PLLM_DEFAULT_VALUE << AW_PID_2113_PLLM_START_BIT)

/* default value of SYSINTM (0x03) */
#define AW_PID_2113_SYSINTM_DEFAULT		(0xFFFF)

/* SYSCTRL (0x04) detail */
/* ULS_HMUTE bit 14 (SYSCTRL 0x04) */
#define AW_PID_2113_ULS_HMUTE_START_BIT	(14)
#define AW_PID_2113_ULS_HMUTE_BITS_LEN	(1)
#define AW_PID_2113_ULS_HMUTE_MASK	\
	(~(((1<<AW_PID_2113_ULS_HMUTE_BITS_LEN)-1) << AW_PID_2113_ULS_HMUTE_START_BIT))

#define AW_PID_2113_ULS_HMUTE_DISABLE	(0)
#define AW_PID_2113_ULS_HMUTE_DISABLE_VALUE	\
	(AW_PID_2113_ULS_HMUTE_DISABLE << AW_PID_2113_ULS_HMUTE_START_BIT)

#define AW_PID_2113_ULS_HMUTE_ENABLE	(1)
#define AW_PID_2113_ULS_HMUTE_ENABLE_VALUE	\
	(AW_PID_2113_ULS_HMUTE_ENABLE << AW_PID_2113_ULS_HMUTE_START_BIT)

#define AW_PID_2113_ULS_HMUTE_DEFAULT_VALUE	(0)
#define AW_PID_2113_ULS_HMUTE_DEFAULT	\
	(AW_PID_2113_ULS_HMUTE_DEFAULT_VALUE << AW_PID_2113_ULS_HMUTE_START_BIT)

/* SPK_GAIN bit 13:12 (SYSCTRL 0x04) */
#define AW_PID_2113_SPK_GAIN_START_BIT	(12)
#define AW_PID_2113_SPK_GAIN_BITS_LEN	(2)
#define AW_PID_2113_SPK_GAIN_MASK	\
	(~(((1<<AW_PID_2113_SPK_GAIN_BITS_LEN)-1) << AW_PID_2113_SPK_GAIN_START_BIT))

#define AW_PID_2113_SPK_GAIN_4_AV	(0)
#define AW_PID_2113_SPK_GAIN_4_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_4_AV << AW_PID_2113_SPK_GAIN_START_BIT)

#define AW_PID_2113_SPK_GAIN_6_AV	(1)
#define AW_PID_2113_SPK_GAIN_6_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_6_AV << AW_PID_2113_SPK_GAIN_START_BIT)

#define AW_PID_2113_SPK_GAIN_6P8_AV	(2)
#define AW_PID_2113_SPK_GAIN_6P8_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_6P8_AV << AW_PID_2113_SPK_GAIN_START_BIT)

#define AW_PID_2113_SPK_GAIN_12_AV	(3)
#define AW_PID_2113_SPK_GAIN_12_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_12_AV << AW_PID_2113_SPK_GAIN_START_BIT)

#define AW_PID_2113_SPK_GAIN_DEFAULT_VALUE	(3)
#define AW_PID_2113_SPK_GAIN_DEFAULT	\
	(AW_PID_2113_SPK_GAIN_DEFAULT_VALUE << AW_PID_2113_SPK_GAIN_START_BIT)

/* RMSE bit 11 (SYSCTRL 0x04) */
#define AW_PID_2113_RMSE_START_BIT	(11)
#define AW_PID_2113_RMSE_BITS_LEN	(1)
#define AW_PID_2113_RMSE_MASK	\
	(~(((1<<AW_PID_2113_RMSE_BITS_LEN)-1) << AW_PID_2113_RMSE_START_BIT))

#define AW_PID_2113_RMSE_PEAK_AGC	(0)
#define AW_PID_2113_RMSE_PEAK_AGC_VALUE	\
	(AW_PID_2113_RMSE_PEAK_AGC << AW_PID_2113_RMSE_START_BIT)

#define AW_PID_2113_RMSE_RMS_AGC	(1)
#define AW_PID_2113_RMSE_RMS_AGC_VALUE	\
	(AW_PID_2113_RMSE_RMS_AGC << AW_PID_2113_RMSE_START_BIT)

#define AW_PID_2113_RMSE_DEFAULT_VALUE	(0)
#define AW_PID_2113_RMSE_DEFAULT	\
	(AW_PID_2113_RMSE_DEFAULT_VALUE << AW_PID_2113_RMSE_START_BIT)

/* HAGCE bit 10 (SYSCTRL 0x04) */
#define AW_PID_2113_HAGCE_START_BIT	(10)
#define AW_PID_2113_HAGCE_BITS_LEN	(1)
#define AW_PID_2113_HAGCE_MASK	\
	(~(((1<<AW_PID_2113_HAGCE_BITS_LEN)-1) << AW_PID_2113_HAGCE_START_BIT))

#define AW_PID_2113_HAGCE_DISABLE	(0)
#define AW_PID_2113_HAGCE_DISABLE_VALUE	\
	(AW_PID_2113_HAGCE_DISABLE << AW_PID_2113_HAGCE_START_BIT)

#define AW_PID_2113_HAGCE_ENABLE	(1)
#define AW_PID_2113_HAGCE_ENABLE_VALUE	\
	(AW_PID_2113_HAGCE_ENABLE << AW_PID_2113_HAGCE_START_BIT)

#define AW_PID_2113_HAGCE_DEFAULT_VALUE	(0)
#define AW_PID_2113_HAGCE_DEFAULT	\
	(AW_PID_2113_HAGCE_DEFAULT_VALUE << AW_PID_2113_HAGCE_START_BIT)

/* HDCCE bit 9 (SYSCTRL 0x04) */
#define AW_PID_2113_HDCCE_START_BIT	(9)
#define AW_PID_2113_HDCCE_BITS_LEN	(1)
#define AW_PID_2113_HDCCE_MASK	\
	(~(((1<<AW_PID_2113_HDCCE_BITS_LEN)-1) << AW_PID_2113_HDCCE_START_BIT))

#define AW_PID_2113_HDCCE_DISABLE	(0)
#define AW_PID_2113_HDCCE_DISABLE_VALUE	\
	(AW_PID_2113_HDCCE_DISABLE << AW_PID_2113_HDCCE_START_BIT)

#define AW_PID_2113_HDCCE_ENABLE	(1)
#define AW_PID_2113_HDCCE_ENABLE_VALUE	\
	(AW_PID_2113_HDCCE_ENABLE << AW_PID_2113_HDCCE_START_BIT)

#define AW_PID_2113_HDCCE_DEFAULT_VALUE	(1)
#define AW_PID_2113_HDCCE_DEFAULT	\
	(AW_PID_2113_HDCCE_DEFAULT_VALUE << AW_PID_2113_HDCCE_START_BIT)

/* HMUTE bit 8 (SYSCTRL 0x04) */
#define AW_PID_2113_HMUTE_START_BIT	(8)
#define AW_PID_2113_HMUTE_BITS_LEN	(1)
#define AW_PID_2113_HMUTE_MASK	\
	(~(((1<<AW_PID_2113_HMUTE_BITS_LEN)-1) << AW_PID_2113_HMUTE_START_BIT))

#define AW_PID_2113_HMUTE_DISABLE	(0)
#define AW_PID_2113_HMUTE_DISABLE_VALUE	\
	(AW_PID_2113_HMUTE_DISABLE << AW_PID_2113_HMUTE_START_BIT)

#define AW_PID_2113_HMUTE_ENABLE	(1)
#define AW_PID_2113_HMUTE_ENABLE_VALUE	\
	(AW_PID_2113_HMUTE_ENABLE << AW_PID_2113_HMUTE_START_BIT)

#define AW_PID_2113_HMUTE_DEFAULT_VALUE	(1)
#define AW_PID_2113_HMUTE_DEFAULT	\
	(AW_PID_2113_HMUTE_DEFAULT_VALUE << AW_PID_2113_HMUTE_START_BIT)

/* EN_TRAN bit 7 (SYSCTRL 0x04) */
#define AW_PID_2113_EN_TRAN_START_BIT	(7)
#define AW_PID_2113_EN_TRAN_BITS_LEN	(1)
#define AW_PID_2113_EN_TRAN_MASK	\
	(~(((1<<AW_PID_2113_EN_TRAN_BITS_LEN)-1) << AW_PID_2113_EN_TRAN_START_BIT))

#define AW_PID_2113_EN_TRAN_SPK	(0)
#define AW_PID_2113_EN_TRAN_SPK_VALUE	\
	(AW_PID_2113_EN_TRAN_SPK << AW_PID_2113_EN_TRAN_START_BIT)

#define AW_PID_2113_EN_TRAN_RCV	(1)
#define AW_PID_2113_EN_TRAN_RCV_VALUE	\
	(AW_PID_2113_EN_TRAN_RCV << AW_PID_2113_EN_TRAN_START_BIT)

#define AW_PID_2113_EN_TRAN_DEFAULT_VALUE	(0)
#define AW_PID_2113_EN_TRAN_DEFAULT	\
	(AW_PID_2113_EN_TRAN_DEFAULT_VALUE << AW_PID_2113_EN_TRAN_START_BIT)

/* I2SEN bit 6 (SYSCTRL 0x04) */
#define AW_PID_2113_I2SEN_START_BIT	(6)
#define AW_PID_2113_I2SEN_BITS_LEN	(1)
#define AW_PID_2113_I2SEN_MASK	\
	(~(((1<<AW_PID_2113_I2SEN_BITS_LEN)-1) << AW_PID_2113_I2SEN_START_BIT))

#define AW_PID_2113_I2SEN_DISABLE	(0)
#define AW_PID_2113_I2SEN_DISABLE_VALUE	\
	(AW_PID_2113_I2SEN_DISABLE << AW_PID_2113_I2SEN_START_BIT)

#define AW_PID_2113_I2SEN_ENABLE	(1)
#define AW_PID_2113_I2SEN_ENABLE_VALUE	\
	(AW_PID_2113_I2SEN_ENABLE << AW_PID_2113_I2SEN_START_BIT)

#define AW_PID_2113_I2SEN_DEFAULT_VALUE	(1)
#define AW_PID_2113_I2SEN_DEFAULT	\
	(AW_PID_2113_I2SEN_DEFAULT_VALUE << AW_PID_2113_I2SEN_START_BIT)

/* WSINV bit 5 (SYSCTRL 0x04) */
#define AW_PID_2113_WSINV_START_BIT	(5)
#define AW_PID_2113_WSINV_BITS_LEN	(1)
#define AW_PID_2113_WSINV_MASK	\
	(~(((1<<AW_PID_2113_WSINV_BITS_LEN)-1) << AW_PID_2113_WSINV_START_BIT))

#define AW_PID_2113_WSINV_NOT_SWITCH	(0)
#define AW_PID_2113_WSINV_NOT_SWITCH_VALUE	\
	(AW_PID_2113_WSINV_NOT_SWITCH << AW_PID_2113_WSINV_START_BIT)

#define AW_PID_2113_WSINV_SWITCH	(1)
#define AW_PID_2113_WSINV_SWITCH_VALUE	\
	(AW_PID_2113_WSINV_SWITCH << AW_PID_2113_WSINV_START_BIT)

#define AW_PID_2113_WSINV_DEFAULT_VALUE	(0)
#define AW_PID_2113_WSINV_DEFAULT	\
	(AW_PID_2113_WSINV_DEFAULT_VALUE << AW_PID_2113_WSINV_START_BIT)

/* BCKINV bit 4 (SYSCTRL 0x04) */
#define AW_PID_2113_BCKINV_START_BIT	(4)
#define AW_PID_2113_BCKINV_BITS_LEN	(1)
#define AW_PID_2113_BCKINV_MASK	\
	(~(((1<<AW_PID_2113_BCKINV_BITS_LEN)-1) << AW_PID_2113_BCKINV_START_BIT))

#define AW_PID_2113_BCKINV_NOT_INVERT	(0)
#define AW_PID_2113_BCKINV_NOT_INVERT_VALUE	\
	(AW_PID_2113_BCKINV_NOT_INVERT << AW_PID_2113_BCKINV_START_BIT)

#define AW_PID_2113_BCKINV_INVERTED	(1)
#define AW_PID_2113_BCKINV_INVERTED_VALUE	\
	(AW_PID_2113_BCKINV_INVERTED << AW_PID_2113_BCKINV_START_BIT)

#define AW_PID_2113_BCKINV_DEFAULT_VALUE	(0)
#define AW_PID_2113_BCKINV_DEFAULT	\
	(AW_PID_2113_BCKINV_DEFAULT_VALUE << AW_PID_2113_BCKINV_START_BIT)

/* IPLL bit 3 (SYSCTRL 0x04) */
#define AW_PID_2113_IPLL_START_BIT	(3)
#define AW_PID_2113_IPLL_BITS_LEN	(1)
#define AW_PID_2113_IPLL_MASK	\
	(~(((1<<AW_PID_2113_IPLL_BITS_LEN)-1) << AW_PID_2113_IPLL_START_BIT))

#define AW_PID_2113_IPLL_BCK	(0)
#define AW_PID_2113_IPLL_BCK_VALUE	\
	(AW_PID_2113_IPLL_BCK << AW_PID_2113_IPLL_START_BIT)

#define AW_PID_2113_IPLL_WCK	(1)
#define AW_PID_2113_IPLL_WCK_VALUE	\
	(AW_PID_2113_IPLL_WCK << AW_PID_2113_IPLL_START_BIT)

#define AW_PID_2113_IPLL_DEFAULT_VALUE	(0)
#define AW_PID_2113_IPLL_DEFAULT	\
	(AW_PID_2113_IPLL_DEFAULT_VALUE << AW_PID_2113_IPLL_START_BIT)

/* AMPPD bit 1 (SYSCTRL 0x04) */
#define AW_PID_2113_AMPPD_START_BIT	(1)
#define AW_PID_2113_AMPPD_BITS_LEN	(1)
#define AW_PID_2113_AMPPD_MASK	\
	(~(((1<<AW_PID_2113_AMPPD_BITS_LEN)-1) << AW_PID_2113_AMPPD_START_BIT))

#define AW_PID_2113_AMPPD_WORKING	(0)
#define AW_PID_2113_AMPPD_WORKING_VALUE	\
	(AW_PID_2113_AMPPD_WORKING << AW_PID_2113_AMPPD_START_BIT)

#define AW_PID_2113_AMPPD_POWER_DOWN	(1)
#define AW_PID_2113_AMPPD_POWER_DOWN_VALUE	\
	(AW_PID_2113_AMPPD_POWER_DOWN << AW_PID_2113_AMPPD_START_BIT)

#define AW_PID_2113_AMPPD_DEFAULT_VALUE	(1)
#define AW_PID_2113_AMPPD_DEFAULT	\
	(AW_PID_2113_AMPPD_DEFAULT_VALUE << AW_PID_2113_AMPPD_START_BIT)

/* PWDN bit 0 (SYSCTRL 0x04) */
#define AW_PID_2113_PWDN_START_BIT	(0)
#define AW_PID_2113_PWDN_BITS_LEN	(1)
#define AW_PID_2113_PWDN_MASK	\
	(~(((1<<AW_PID_2113_PWDN_BITS_LEN)-1) << AW_PID_2113_PWDN_START_BIT))

#define AW_PID_2113_PWDN_WORKING	(0)
#define AW_PID_2113_PWDN_WORKING_VALUE	\
	(AW_PID_2113_PWDN_WORKING << AW_PID_2113_PWDN_START_BIT)

#define AW_PID_2113_PWDN_POWER_DOWN	(1)
#define AW_PID_2113_PWDN_POWER_DOWN_VALUE	\
	(AW_PID_2113_PWDN_POWER_DOWN << AW_PID_2113_PWDN_START_BIT)

#define AW_PID_2113_PWDN_DEFAULT_VALUE	(1)
#define AW_PID_2113_PWDN_DEFAULT	\
	(AW_PID_2113_PWDN_DEFAULT_VALUE << AW_PID_2113_PWDN_START_BIT)

/* default value of SYSCTRL (0x04) */
/* #define AW_PID_2113_SYSCTRL_DEFAULT		(0x3343) */

/* SYSCTRL2 (0x05) detail */
/* ULS_MODE bit 12 (SYSCTRL2 0x05) */
#define AW_PID_2113_ULS_MODE_START_BIT	(12)
#define AW_PID_2113_ULS_MODE_BITS_LEN	(1)
#define AW_PID_2113_ULS_MODE_MASK	\
	(~(((1<<AW_PID_2113_ULS_MODE_BITS_LEN)-1) << AW_PID_2113_ULS_MODE_START_BIT))

#define AW_PID_2113_ULS_MODE_LEGACY	(0)
#define AW_PID_2113_ULS_MODE_LEGACY_VALUE	\
	(AW_PID_2113_ULS_MODE_LEGACY << AW_PID_2113_ULS_MODE_START_BIT)

#define AW_PID_2113_ULS_MODE_TDM	(1)
#define AW_PID_2113_ULS_MODE_TDM_VALUE	\
	(AW_PID_2113_ULS_MODE_TDM << AW_PID_2113_ULS_MODE_START_BIT)

#define AW_PID_2113_ULS_MODE_DEFAULT_VALUE	(0)
#define AW_PID_2113_ULS_MODE_DEFAULT	\
	(AW_PID_2113_ULS_MODE_DEFAULT_VALUE << AW_PID_2113_ULS_MODE_START_BIT)

/* INTMODE bit 11 (SYSCTRL2 0x05) */
#define AW_PID_2113_INTMODE_START_BIT	(11)
#define AW_PID_2113_INTMODE_BITS_LEN	(1)
#define AW_PID_2113_INTMODE_MASK	\
	(~(((1<<AW_PID_2113_INTMODE_BITS_LEN)-1) << AW_PID_2113_INTMODE_START_BIT))

#define AW_PID_2113_INTMODE_OPENMINUS_DRAIN	(0)
#define AW_PID_2113_INTMODE_OPENMINUS_DRAIN_VALUE	\
	(AW_PID_2113_INTMODE_OPENMINUS_DRAIN << AW_PID_2113_INTMODE_START_BIT)

#define AW_PID_2113_INTMODE_PUSHPULL	(1)
#define AW_PID_2113_INTMODE_PUSHPULL_VALUE	\
	(AW_PID_2113_INTMODE_PUSHPULL << AW_PID_2113_INTMODE_START_BIT)

#define AW_PID_2113_INTMODE_DEFAULT_VALUE	(0)
#define AW_PID_2113_INTMODE_DEFAULT	\
	(AW_PID_2113_INTMODE_DEFAULT_VALUE << AW_PID_2113_INTMODE_START_BIT)

/* INTN bit 10 (SYSCTRL2 0x05) */
#define AW_PID_2113_INTN_START_BIT	(10)
#define AW_PID_2113_INTN_BITS_LEN	(1)
#define AW_PID_2113_INTN_MASK	\
	(~(((1<<AW_PID_2113_INTN_BITS_LEN)-1) << AW_PID_2113_INTN_START_BIT))

#define AW_PID_2113_INTN_SYSINT	(0)
#define AW_PID_2113_INTN_SYSINT_VALUE	\
	(AW_PID_2113_INTN_SYSINT << AW_PID_2113_INTN_START_BIT)

#define AW_PID_2113_INTN_SYSST	(1)
#define AW_PID_2113_INTN_SYSST_VALUE	\
	(AW_PID_2113_INTN_SYSST << AW_PID_2113_INTN_START_BIT)

#define AW_PID_2113_INTN_DEFAULT_VALUE	(0)
#define AW_PID_2113_INTN_DEFAULT	\
	(AW_PID_2113_INTN_DEFAULT_VALUE << AW_PID_2113_INTN_START_BIT)

/* VOL bit 9:0 (SYSCTRL2 0x05) */
#define AW_PID_2113_VOL_START_BIT	(0)
#define AW_PID_2113_VOL_BITS_LEN	(10)
#define AW_PID_2113_VOL_MASK	\
	(~(((1<<AW_PID_2113_VOL_BITS_LEN)-1) << AW_PID_2113_VOL_START_BIT))

#define AW_PID_2113_VOL_DEFAULT_VALUE	(0)
#define AW_PID_2113_VOL_DEFAULT	\
	(AW_PID_2113_VOL_DEFAULT_VALUE << AW_PID_2113_VOL_START_BIT)

#define AW_PID_2113_MUTE_VOL	(90 * 8)
#define AW_PID_2113_VOL_STEP_DB	(6 * 8)
/* default value of SYSCTRL2 (0x05) */
/* #define AW_PID_2113_SYSCTRL2_DEFAULT		(0x0000) */

/* I2SCTRL1 (0x06) detail */
/* CFSEL bit 14:12 (I2SCTRL1 0x06) */
#define AW_PID_2113_CFSEL_START_BIT	(12)
#define AW_PID_2113_CFSEL_BITS_LEN	(3)
#define AW_PID_2113_CFSEL_MASK	\
	(~(((1<<AW_PID_2113_CFSEL_BITS_LEN)-1) << AW_PID_2113_CFSEL_START_BIT))

#define AW_PID_2113_CFSEL_HAGC	(0)
#define AW_PID_2113_CFSEL_HAGC_VALUE	\
	(AW_PID_2113_CFSEL_HAGC << AW_PID_2113_CFSEL_START_BIT)

#define AW_PID_2113_CFSEL_SAR_ADO	(1)
#define AW_PID_2113_CFSEL_SAR_ADO_VALUE	\
	(AW_PID_2113_CFSEL_SAR_ADO << AW_PID_2113_CFSEL_START_BIT)

#define AW_PID_2113_CFSEL_IVBT	(2)
#define AW_PID_2113_CFSEL_IVBT_VALUE	\
	(AW_PID_2113_CFSEL_IVBT << AW_PID_2113_CFSEL_START_BIT)

#define AW_PID_2113_CFSEL_IV_SENSE_100_MPD_LP_101_ADP_BOOST_OTHERS_RESERVED	(3)
#define AW_PID_2113_CFSEL_IV_SENSE_100_MPD_LP_101_ADP_BOOST_OTHERS_RESERVED_VALUE	\
	(AW_PID_2113_CFSEL_IV_SENSE_100_MPD_LP_101_ADP_BOOST_OTHERS_RESERVED << AW_PID_2113_CFSEL_START_BIT)

#define AW_PID_2113_CFSEL_DEFAULT_VALUE	(0)
#define AW_PID_2113_CFSEL_DEFAULT	\
	(AW_PID_2113_CFSEL_DEFAULT_VALUE << AW_PID_2113_CFSEL_START_BIT)

/* CHSEL bit 11:10 (I2SCTRL1 0x06) */
#define AW_PID_2113_CHSEL_START_BIT	(10)
#define AW_PID_2113_CHSEL_BITS_LEN	(2)
#define AW_PID_2113_CHSEL_MASK	\
	(~(((1<<AW_PID_2113_CHSEL_BITS_LEN)-1) << AW_PID_2113_CHSEL_START_BIT))

#define AW_PID_2113_CHSEL_RESERVED	(0)
#define AW_PID_2113_CHSEL_RESERVED_VALUE	\
	(AW_PID_2113_CHSEL_RESERVED << AW_PID_2113_CHSEL_START_BIT)

#define AW_PID_2113_CHSEL_LEFT	(1)
#define AW_PID_2113_CHSEL_LEFT_VALUE	\
	(AW_PID_2113_CHSEL_LEFT << AW_PID_2113_CHSEL_START_BIT)

#define AW_PID_2113_CHSEL_RIGHT	(2)
#define AW_PID_2113_CHSEL_RIGHT_VALUE	\
	(AW_PID_2113_CHSEL_RIGHT << AW_PID_2113_CHSEL_START_BIT)

#define AW_PID_2113_CHSEL_MONO	(3)
#define AW_PID_2113_CHSEL_MONO_VALUE	\
	(AW_PID_2113_CHSEL_MONO << AW_PID_2113_CHSEL_START_BIT)

#define AW_PID_2113_CHSEL_DEFAULT_VALUE	(1)
#define AW_PID_2113_CHSEL_DEFAULT	\
	(AW_PID_2113_CHSEL_DEFAULT_VALUE << AW_PID_2113_CHSEL_START_BIT)

/* I2SMD bit 9:8 (I2SCTRL1 0x06) */
#define AW_PID_2113_I2SMD_START_BIT	(8)
#define AW_PID_2113_I2SMD_BITS_LEN	(2)
#define AW_PID_2113_I2SMD_MASK	\
	(~(((1<<AW_PID_2113_I2SMD_BITS_LEN)-1) << AW_PID_2113_I2SMD_START_BIT))

#define AW_PID_2113_I2SMD_PHILIP_STANDARD	(0)
#define AW_PID_2113_I2SMD_PHILIP_STANDARD_VALUE	\
	(AW_PID_2113_I2SMD_PHILIP_STANDARD << AW_PID_2113_I2SMD_START_BIT)

#define AW_PID_2113_I2SMD_MSB_JUSTIFIED	(1)
#define AW_PID_2113_I2SMD_MSB_JUSTIFIED_VALUE	\
	(AW_PID_2113_I2SMD_MSB_JUSTIFIED << AW_PID_2113_I2SMD_START_BIT)

#define AW_PID_2113_I2SMD_LSB_JUSTIFIED	(2)
#define AW_PID_2113_I2SMD_LSB_JUSTIFIED_VALUE	\
	(AW_PID_2113_I2SMD_LSB_JUSTIFIED << AW_PID_2113_I2SMD_START_BIT)

#define AW_PID_2113_I2SMD_RESERVED	(3)
#define AW_PID_2113_I2SMD_RESERVED_VALUE	\
	(AW_PID_2113_I2SMD_RESERVED << AW_PID_2113_I2SMD_START_BIT)

#define AW_PID_2113_I2SMD_DEFAULT_VALUE	(0)
#define AW_PID_2113_I2SMD_DEFAULT	\
	(AW_PID_2113_I2SMD_DEFAULT_VALUE << AW_PID_2113_I2SMD_START_BIT)

/* I2SFS bit 7:6 (I2SCTRL1 0x06) */
#define AW_PID_2113_I2SFS_START_BIT	(6)
#define AW_PID_2113_I2SFS_BITS_LEN	(2)
#define AW_PID_2113_I2SFS_MASK	\
	(~(((1<<AW_PID_2113_I2SFS_BITS_LEN)-1) << AW_PID_2113_I2SFS_START_BIT))

#define AW_PID_2113_I2SFS_16_BITS	(0)
#define AW_PID_2113_I2SFS_16_BITS_VALUE	\
	(AW_PID_2113_I2SFS_16_BITS << AW_PID_2113_I2SFS_START_BIT)

#define AW_PID_2113_I2SFS_20_BITS	(1)
#define AW_PID_2113_I2SFS_20_BITS_VALUE	\
	(AW_PID_2113_I2SFS_20_BITS << AW_PID_2113_I2SFS_START_BIT)

#define AW_PID_2113_I2SFS_24_BITS	(2)
#define AW_PID_2113_I2SFS_24_BITS_VALUE	\
	(AW_PID_2113_I2SFS_24_BITS << AW_PID_2113_I2SFS_START_BIT)

#define AW_PID_2113_I2SFS_32_BITS	(3)
#define AW_PID_2113_I2SFS_32_BITS_VALUE	\
	(AW_PID_2113_I2SFS_32_BITS << AW_PID_2113_I2SFS_START_BIT)

#define AW_PID_2113_I2SFS_DEFAULT_VALUE	(3)
#define AW_PID_2113_I2SFS_DEFAULT	\
	(AW_PID_2113_I2SFS_DEFAULT_VALUE << AW_PID_2113_I2SFS_START_BIT)

/* I2SBCK bit 5:4 (I2SCTRL1 0x06) */
#define AW_PID_2113_I2SBCK_START_BIT	(4)
#define AW_PID_2113_I2SBCK_BITS_LEN	(2)
#define AW_PID_2113_I2SBCK_MASK	\
	(~(((1<<AW_PID_2113_I2SBCK_BITS_LEN)-1) << AW_PID_2113_I2SBCK_START_BIT))

#define AW_PID_2113_I2SBCK_32FS	(0)
#define AW_PID_2113_I2SBCK_32FS_VALUE	\
	(AW_PID_2113_I2SBCK_32FS << AW_PID_2113_I2SBCK_START_BIT)

#define AW_PID_2113_I2SBCK_48FS	(1)
#define AW_PID_2113_I2SBCK_48FS_VALUE	\
	(AW_PID_2113_I2SBCK_48FS << AW_PID_2113_I2SBCK_START_BIT)

#define AW_PID_2113_I2SBCK_64FS	(2)
#define AW_PID_2113_I2SBCK_64FS_VALUE	\
	(AW_PID_2113_I2SBCK_64FS << AW_PID_2113_I2SBCK_START_BIT)

#define AW_PID_2113_I2SBCK_RESERVED	(3)
#define AW_PID_2113_I2SBCK_RESERVED_VALUE	\
	(AW_PID_2113_I2SBCK_RESERVED << AW_PID_2113_I2SBCK_START_BIT)

#define AW_PID_2113_I2SBCK_DEFAULT_VALUE	(2)
#define AW_PID_2113_I2SBCK_DEFAULT	\
	(AW_PID_2113_I2SBCK_DEFAULT_VALUE << AW_PID_2113_I2SBCK_START_BIT)

/* I2SSR bit 3:0 (I2SCTRL1 0x06) */
#define AW_PID_2113_I2SSR_START_BIT	(0)
#define AW_PID_2113_I2SSR_BITS_LEN	(4)
#define AW_PID_2113_I2SSR_MASK	\
	(~(((1<<AW_PID_2113_I2SSR_BITS_LEN)-1) << AW_PID_2113_I2SSR_START_BIT))

#define AW_PID_2113_I2SSR_8_KHZ	(0)
#define AW_PID_2113_I2SSR_8_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_8_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_11_KHZ	(1)
#define AW_PID_2113_I2SSR_11_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_11_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_12_KHZ	(2)
#define AW_PID_2113_I2SSR_12_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_12_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_16_KHZ	(3)
#define AW_PID_2113_I2SSR_16_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_16_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_22_KHZ	(4)
#define AW_PID_2113_I2SSR_22_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_22_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_24_KHZ	(5)
#define AW_PID_2113_I2SSR_24_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_24_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_32_KHZ	(6)
#define AW_PID_2113_I2SSR_32_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_32_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_44_KHZ	(7)
#define AW_PID_2113_I2SSR_44_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_44_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_48_KHZ	(8)
#define AW_PID_2113_I2SSR_48_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_48_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_96_KHZ	(9)
#define AW_PID_2113_I2SSR_96_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_96_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_192_KHZ	(10)
#define AW_PID_2113_I2SSR_192_KHZ_VALUE	\
	(AW_PID_2113_I2SSR_192_KHZ << AW_PID_2113_I2SSR_START_BIT)

#define AW_PID_2113_I2SSR_DEFAULT_VALUE	(8)
#define AW_PID_2113_I2SSR_DEFAULT	\
	(AW_PID_2113_I2SSR_DEFAULT_VALUE << AW_PID_2113_I2SSR_START_BIT)

/* default value of I2SCTRL1 (0x06) */
/* #define AW_PID_2113_I2SCTRL1_DEFAULT		(0x04E8) */

/* I2SCTRL2 (0x07) detail */
/* SLOT_NUM bit 14:12 (I2SCTRL2 0x07) */
#define AW_PID_2113_SLOT_NUM_START_BIT	(12)
#define AW_PID_2113_SLOT_NUM_BITS_LEN	(3)
#define AW_PID_2113_SLOT_NUM_MASK	\
	(~(((1<<AW_PID_2113_SLOT_NUM_BITS_LEN)-1) << AW_PID_2113_SLOT_NUM_START_BIT))

#define AW_PID_2113_SLOT_NUM_I2S_MODE	(0)
#define AW_PID_2113_SLOT_NUM_I2S_MODE_VALUE	\
	(AW_PID_2113_SLOT_NUM_I2S_MODE << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM1S	(1)
#define AW_PID_2113_SLOT_NUM_TDM1S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM1S << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM2S	(2)
#define AW_PID_2113_SLOT_NUM_TDM2S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM2S << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM4S	(3)
#define AW_PID_2113_SLOT_NUM_TDM4S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM4S << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM6S	(4)
#define AW_PID_2113_SLOT_NUM_TDM6S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM6S << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM8S	(5)
#define AW_PID_2113_SLOT_NUM_TDM8S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM8S << AW_PID_2113_SLOT_NUM_START_BIT)

#define AW_PID_2113_SLOT_NUM_TDM16S	(6)
#define AW_PID_2113_SLOT_NUM_TDM16S_VALUE	\
	(AW_PID_2113_SLOT_NUM_TDM16S << AW_PID_2113_SLOT_NUM_START_BIT)

/*
 *#define AW_PID_2113_SLOT_NUM_TDM16S	(7)
 *#define AW_PID_2113_SLOT_NUM_TDM16S_VALUE	\
 *	(AW_PID_2113_SLOT_NUM_TDM16S << AW_PID_2113_SLOT_NUM_START_BIT)
 */

#define AW_PID_2113_SLOT_NUM_DEFAULT_VALUE	(0)
#define AW_PID_2113_SLOT_NUM_DEFAULT	\
	(AW_PID_2113_SLOT_NUM_DEFAULT_VALUE << AW_PID_2113_SLOT_NUM_START_BIT)

/* I2S_TX_SLOTVLD bit 11:8 (I2SCTRL2 0x07) */
#define AW_PID_2113_I2S_TX_SLOTVLD_START_BIT	(8)
#define AW_PID_2113_I2S_TX_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2113_I2S_TX_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2113_I2S_TX_SLOTVLD_BITS_LEN)-1) << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT))

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_0	(0)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_0 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_1	(1)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_1 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_2	(2)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_2 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_3	(3)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_3 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_4	(4)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_4_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_4 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_5	(5)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_5_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_5 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_6	(6)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_6_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_6 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_15	(15)
#define AW_PID_2113_I2S_TX_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2113_I2S_TX_SLOTVLD_SLOT_15 << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_TX_SLOTVLD_DEFAULT_VALUE	(0)
#define AW_PID_2113_I2S_TX_SLOTVLD_DEFAULT	\
	(AW_PID_2113_I2S_TX_SLOTVLD_DEFAULT_VALUE << AW_PID_2113_I2S_TX_SLOTVLD_START_BIT)

/* I2S_RXR_SLOTVLD bit 7:4 (I2SCTRL2 0x07) */
#define AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT	(4)
#define AW_PID_2113_I2S_RXR_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2113_I2S_RXR_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2113_I2S_RXR_SLOTVLD_BITS_LEN)-1) << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT))

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_0	(0)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_0 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_1	(1)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_1 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_2	(2)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_2 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_3	(3)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_3 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_4	(4)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_4_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_4 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_5	(5)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_5_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_5 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_6	(6)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_6_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_6 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_15	(15)
#define AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_SLOT_15 << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXR_SLOTVLD_DEFAULT_VALUE	(1)
#define AW_PID_2113_I2S_RXR_SLOTVLD_DEFAULT	\
	(AW_PID_2113_I2S_RXR_SLOTVLD_DEFAULT_VALUE << AW_PID_2113_I2S_RXR_SLOTVLD_START_BIT)

/* I2S_RXL_SLOTVLD bit 3:0 (I2SCTRL2 0x07) */
#define AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT	(0)
#define AW_PID_2113_I2S_RXL_SLOTVLD_BITS_LEN	(4)
#define AW_PID_2113_I2S_RXL_SLOTVLD_MASK	\
	(~(((1<<AW_PID_2113_I2S_RXL_SLOTVLD_BITS_LEN)-1) << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT))

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_0	(0)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_0_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_0 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_1	(1)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_1_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_1 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_2	(2)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_2_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_2 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_3	(3)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_3_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_3 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_4	(4)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_4_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_4 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_5	(5)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_5_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_5 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_6	(6)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_6_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_6 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_15	(15)
#define AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_15_VALUE	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_SLOT_15 << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

#define AW_PID_2113_I2S_RXL_SLOTVLD_DEFAULT_VALUE	(0)
#define AW_PID_2113_I2S_RXL_SLOTVLD_DEFAULT	\
	(AW_PID_2113_I2S_RXL_SLOTVLD_DEFAULT_VALUE << AW_PID_2113_I2S_RXL_SLOTVLD_START_BIT)

/* default value of I2SCTRL2 (0x07) */
/* #define AW_PID_2113_I2SCTRL2_DEFAULT		(0x0010) */

/* I2SCTRL3 (0x08) detail */
/* FSYNC_TYPE bit 7 (I2SCTRL3 0x08) */
#define AW_PID_2113_FSYNC_TYPE_START_BIT	(7)
#define AW_PID_2113_FSYNC_TYPE_BITS_LEN	(1)
#define AW_PID_2113_FSYNC_TYPE_MASK	\
	(~(((1<<AW_PID_2113_FSYNC_TYPE_BITS_LEN)-1) << AW_PID_2113_FSYNC_TYPE_START_BIT))

#define AW_PID_2113_FSYNC_TYPE_ONEMINUS_SLOT	(0)
#define AW_PID_2113_FSYNC_TYPE_ONEMINUS_SLOT_VALUE	\
	(AW_PID_2113_FSYNC_TYPE_ONEMINUS_SLOT << AW_PID_2113_FSYNC_TYPE_START_BIT)

#define AW_PID_2113_FSYNC_TYPE_ONEMINUS_BCK	(1)
#define AW_PID_2113_FSYNC_TYPE_ONEMINUS_BCK_VALUE	\
	(AW_PID_2113_FSYNC_TYPE_ONEMINUS_BCK << AW_PID_2113_FSYNC_TYPE_START_BIT)

#define AW_PID_2113_FSYNC_TYPE_DEFAULT_VALUE	(0)
#define AW_PID_2113_FSYNC_TYPE_DEFAULT	\
	(AW_PID_2113_FSYNC_TYPE_DEFAULT_VALUE << AW_PID_2113_FSYNC_TYPE_START_BIT)

/* I2STXEN bit 6 (I2SCTRL3 0x08) */
#define AW_PID_2113_I2STXEN_START_BIT	(6)
#define AW_PID_2113_I2STXEN_BITS_LEN	(1)
#define AW_PID_2113_I2STXEN_MASK	\
	(~(((1<<AW_PID_2113_I2STXEN_BITS_LEN)-1) << AW_PID_2113_I2STXEN_START_BIT))

#define AW_PID_2113_I2STXEN_DISABLE	(0)
#define AW_PID_2113_I2STXEN_DISABLE_VALUE	\
	(AW_PID_2113_I2STXEN_DISABLE << AW_PID_2113_I2STXEN_START_BIT)

#define AW_PID_2113_I2STXEN_ENABLE	(1)
#define AW_PID_2113_I2STXEN_ENABLE_VALUE	\
	(AW_PID_2113_I2STXEN_ENABLE << AW_PID_2113_I2STXEN_START_BIT)

#define AW_PID_2113_I2STXEN_DEFAULT_VALUE	(1)
#define AW_PID_2113_I2STXEN_DEFAULT	\
	(AW_PID_2113_I2STXEN_DEFAULT_VALUE << AW_PID_2113_I2STXEN_START_BIT)

/* DRVSTREN bit 5 (I2SCTRL3 0x08) */
#define AW_PID_2113_DRVSTREN_START_BIT	(5)
#define AW_PID_2113_DRVSTREN_BITS_LEN	(1)
#define AW_PID_2113_DRVSTREN_MASK	\
	(~(((1<<AW_PID_2113_DRVSTREN_BITS_LEN)-1) << AW_PID_2113_DRVSTREN_START_BIT))

#define AW_PID_2113_DRVSTREN_4MA	(0)
#define AW_PID_2113_DRVSTREN_4MA_VALUE	\
	(AW_PID_2113_DRVSTREN_4MA << AW_PID_2113_DRVSTREN_START_BIT)

#define AW_PID_2113_DRVSTREN_12MA	(1)
#define AW_PID_2113_DRVSTREN_12MA_VALUE	\
	(AW_PID_2113_DRVSTREN_12MA << AW_PID_2113_DRVSTREN_START_BIT)

#define AW_PID_2113_DRVSTREN_DEFAULT_VALUE	(1)
#define AW_PID_2113_DRVSTREN_DEFAULT	\
	(AW_PID_2113_DRVSTREN_DEFAULT_VALUE << AW_PID_2113_DRVSTREN_START_BIT)

/* I2SRXEN bit 4 (I2SCTRL3 0x08) */
#define AW_PID_2113_I2SRXEN_START_BIT	(4)
#define AW_PID_2113_I2SRXEN_BITS_LEN	(1)
#define AW_PID_2113_I2SRXEN_MASK	\
	(~(((1<<AW_PID_2113_I2SRXEN_BITS_LEN)-1) << AW_PID_2113_I2SRXEN_START_BIT))

#define AW_PID_2113_I2SRXEN_DISABLE	(0)
#define AW_PID_2113_I2SRXEN_DISABLE_VALUE	\
	(AW_PID_2113_I2SRXEN_DISABLE << AW_PID_2113_I2SRXEN_START_BIT)

#define AW_PID_2113_I2SRXEN_ENABLE	(1)
#define AW_PID_2113_I2SRXEN_ENABLE_VALUE	\
	(AW_PID_2113_I2SRXEN_ENABLE << AW_PID_2113_I2SRXEN_START_BIT)

#define AW_PID_2113_I2SRXEN_DEFAULT_VALUE	(1)
#define AW_PID_2113_I2SRXEN_DEFAULT	\
	(AW_PID_2113_I2SRXEN_DEFAULT_VALUE << AW_PID_2113_I2SRXEN_START_BIT)

/* IV2CH bit 3 (I2SCTRL3 0x08) */
#define AW_PID_2113_IV2CH_START_BIT	(3)
#define AW_PID_2113_IV2CH_BITS_LEN	(1)
#define AW_PID_2113_IV2CH_MASK	\
	(~(((1<<AW_PID_2113_IV2CH_BITS_LEN)-1) << AW_PID_2113_IV2CH_START_BIT))

#define AW_PID_2113_IV2CH_LEGACY	(0)
#define AW_PID_2113_IV2CH_LEGACY_VALUE	\
	(AW_PID_2113_IV2CH_LEGACY << AW_PID_2113_IV2CH_START_BIT)

#define AW_PID_2113_IV2CH_SPECIAL	(1)
#define AW_PID_2113_IV2CH_SPECIAL_VALUE	\
	(AW_PID_2113_IV2CH_SPECIAL << AW_PID_2113_IV2CH_START_BIT)

#define AW_PID_2113_IV2CH_DEFAULT_VALUE	(0)
#define AW_PID_2113_IV2CH_DEFAULT	\
	(AW_PID_2113_IV2CH_DEFAULT_VALUE << AW_PID_2113_IV2CH_START_BIT)

/* I2SDOSEL bit 2 (I2SCTRL3 0x08) */
#define AW_PID_2113_I2SDOSEL_START_BIT	(2)
#define AW_PID_2113_I2SDOSEL_BITS_LEN	(1)
#define AW_PID_2113_I2SDOSEL_MASK	\
	(~(((1<<AW_PID_2113_I2SDOSEL_BITS_LEN)-1) << AW_PID_2113_I2SDOSEL_START_BIT))

#define AW_PID_2113_I2SDOSEL_ZEROS	(0)
#define AW_PID_2113_I2SDOSEL_ZEROS_VALUE	\
	(AW_PID_2113_I2SDOSEL_ZEROS << AW_PID_2113_I2SDOSEL_START_BIT)

#define AW_PID_2113_I2SDOSEL_TXDATA	(1)
#define AW_PID_2113_I2SDOSEL_TXDATA_VALUE	\
	(AW_PID_2113_I2SDOSEL_TXDATA << AW_PID_2113_I2SDOSEL_START_BIT)

#define AW_PID_2113_I2SDOSEL_DEFAULT_VALUE	(1)
#define AW_PID_2113_I2SDOSEL_DEFAULT	\
	(AW_PID_2113_I2SDOSEL_DEFAULT_VALUE << AW_PID_2113_I2SDOSEL_START_BIT)

/* DOHZ bit 1 (I2SCTRL3 0x08) */
#define AW_PID_2113_DOHZ_START_BIT	(1)
#define AW_PID_2113_DOHZ_BITS_LEN	(1)
#define AW_PID_2113_DOHZ_MASK	\
	(~(((1<<AW_PID_2113_DOHZ_BITS_LEN)-1) << AW_PID_2113_DOHZ_START_BIT))

#define AW_PID_2113_DOHZ_ALL	(0)
#define AW_PID_2113_DOHZ_ALL_VALUE	\
	(AW_PID_2113_DOHZ_ALL << AW_PID_2113_DOHZ_START_BIT)

#define AW_PID_2113_DOHZ_HIZ	(1)
#define AW_PID_2113_DOHZ_HIZ_VALUE	\
	(AW_PID_2113_DOHZ_HIZ << AW_PID_2113_DOHZ_START_BIT)

#define AW_PID_2113_DOHZ_DEFAULT_VALUE	(1)
#define AW_PID_2113_DOHZ_DEFAULT	\
	(AW_PID_2113_DOHZ_DEFAULT_VALUE << AW_PID_2113_DOHZ_START_BIT)

/* I2SCHS bit 0 (I2SCTRL3 0x08) */
#define AW_PID_2113_I2SCHS_START_BIT	(0)
#define AW_PID_2113_I2SCHS_BITS_LEN	(1)
#define AW_PID_2113_I2SCHS_MASK	\
	(~(((1<<AW_PID_2113_I2SCHS_BITS_LEN)-1) << AW_PID_2113_I2SCHS_START_BIT))

#define AW_PID_2113_I2SCHS_LEFT	(0)
#define AW_PID_2113_I2SCHS_LEFT_VALUE	\
	(AW_PID_2113_I2SCHS_LEFT << AW_PID_2113_I2SCHS_START_BIT)

#define AW_PID_2113_I2SCHS_RIGHT	(1)
#define AW_PID_2113_I2SCHS_RIGHT_VALUE	\
	(AW_PID_2113_I2SCHS_RIGHT << AW_PID_2113_I2SCHS_START_BIT)

#define AW_PID_2113_I2SCHS_DEFAULT_VALUE	(0)
#define AW_PID_2113_I2SCHS_DEFAULT	\
	(AW_PID_2113_I2SCHS_DEFAULT_VALUE << AW_PID_2113_I2SCHS_START_BIT)

/* default value of I2SCTRL3 (0x08) */
/* #define AW_PID_2113_I2SCTRL3_DEFAULT		(0x0076) */

/* DACCFG1 (0x09) detail */
/* RVTH bit 15:8 (DACCFG1 0x09) */
#define AW_PID_2113_RVTH_START_BIT	(8)
#define AW_PID_2113_RVTH_BITS_LEN	(8)
#define AW_PID_2113_RVTH_MASK	\
	(~(((1<<AW_PID_2113_RVTH_BITS_LEN)-1) << AW_PID_2113_RVTH_START_BIT))

#define AW_PID_2113_RVTH_DEFAULT_VALUE	(0x39)
#define AW_PID_2113_RVTH_DEFAULT	\
	(AW_PID_2113_RVTH_DEFAULT_VALUE << AW_PID_2113_RVTH_START_BIT)

/* AVTH bit 7:0 (DACCFG1 0x09) */
#define AW_PID_2113_AVTH_START_BIT	(0)
#define AW_PID_2113_AVTH_BITS_LEN	(8)
#define AW_PID_2113_AVTH_MASK	\
	(~(((1<<AW_PID_2113_AVTH_BITS_LEN)-1) << AW_PID_2113_AVTH_START_BIT))

#define AW_PID_2113_AVTH_DEFAULT_VALUE	(0x40)
#define AW_PID_2113_AVTH_DEFAULT	\
	(AW_PID_2113_AVTH_DEFAULT_VALUE << AW_PID_2113_AVTH_START_BIT)

/* default value of DACCFG1 (0x09) */
/* #define AW_PID_2113_DACCFG1_DEFAULT		(0x3940) */

/* DACCFG2 (0x0A) detail */
/* ATTH bit 15:0 (DACCFG2 0x0A) */
#define AW_PID_2113_ATTH_START_BIT	(0)
#define AW_PID_2113_ATTH_BITS_LEN	(16)
#define AW_PID_2113_ATTH_MASK	\
	(~(((1<<AW_PID_2113_ATTH_BITS_LEN)-1) << AW_PID_2113_ATTH_START_BIT))

#define AW_PID_2113_ATTH_RESERVED	(0)
#define AW_PID_2113_ATTH_RESERVED_VALUE	\
	(AW_PID_2113_ATTH_RESERVED << AW_PID_2113_ATTH_START_BIT)

#define AW_PID_2113_ATTH_DEFAULT_VALUE	(0x0030)
#define AW_PID_2113_ATTH_DEFAULT	\
	(AW_PID_2113_ATTH_DEFAULT_VALUE << AW_PID_2113_ATTH_START_BIT)

/* default value of DACCFG2 (0x0A) */
/* #define AW_PID_2113_DACCFG2_DEFAULT		(0x0030) */

/* DACCFG3 (0x0B) detail */
/* RTTH bit 15:0 (DACCFG3 0x0B) */
#define AW_PID_2113_RTTH_START_BIT	(0)
#define AW_PID_2113_RTTH_BITS_LEN	(16)
#define AW_PID_2113_RTTH_MASK	\
	(~(((1<<AW_PID_2113_RTTH_BITS_LEN)-1) << AW_PID_2113_RTTH_START_BIT))

#define AW_PID_2113_RTTH_RESERVED	(0)
#define AW_PID_2113_RTTH_RESERVED_VALUE	\
	(AW_PID_2113_RTTH_RESERVED << AW_PID_2113_RTTH_START_BIT)

#define AW_PID_2113_RTTH_DEFAULT_VALUE	(0x01E0)
#define AW_PID_2113_RTTH_DEFAULT	\
	(AW_PID_2113_RTTH_DEFAULT_VALUE << AW_PID_2113_RTTH_START_BIT)

/* default value of DACCFG3 (0x0B) */
/* #define AW_PID_2113_DACCFG3_DEFAULT		(0x01E0) */

/* DACCFG4 (0x0C) detail */
/* IIC_GEN_ADDR bit 15:9 (DACCFG4 0x0C) */
#define AW_PID_2113_IIC_GEN_ADDR_START_BIT	(9)
#define AW_PID_2113_IIC_GEN_ADDR_BITS_LEN	(7)
#define AW_PID_2113_IIC_GEN_ADDR_MASK	\
	(~(((1<<AW_PID_2113_IIC_GEN_ADDR_BITS_LEN)-1) << AW_PID_2113_IIC_GEN_ADDR_START_BIT))

#define AW_PID_2113_IIC_GEN_ADDR_DEFAULT_VALUE	(0x0E)
#define AW_PID_2113_IIC_GEN_ADDR_DEFAULT	\
	(AW_PID_2113_IIC_GEN_ADDR_DEFAULT_VALUE << AW_PID_2113_IIC_GEN_ADDR_START_BIT)

/* IIC_GEN_EN bit 8 (DACCFG4 0x0C) */
#define AW_PID_2113_IIC_GEN_EN_START_BIT	(8)
#define AW_PID_2113_IIC_GEN_EN_BITS_LEN	(1)
#define AW_PID_2113_IIC_GEN_EN_MASK	\
	(~(((1<<AW_PID_2113_IIC_GEN_EN_BITS_LEN)-1) << AW_PID_2113_IIC_GEN_EN_START_BIT))

#define AW_PID_2113_IIC_GEN_EN_DISABLE	(0)
#define AW_PID_2113_IIC_GEN_EN_DISABLE_VALUE	\
	(AW_PID_2113_IIC_GEN_EN_DISABLE << AW_PID_2113_IIC_GEN_EN_START_BIT)

#define AW_PID_2113_IIC_GEN_EN_ENABLE	(1)
#define AW_PID_2113_IIC_GEN_EN_ENABLE_VALUE	\
	(AW_PID_2113_IIC_GEN_EN_ENABLE << AW_PID_2113_IIC_GEN_EN_START_BIT)

#define AW_PID_2113_IIC_GEN_EN_DEFAULT_VALUE	(0)
#define AW_PID_2113_IIC_GEN_EN_DEFAULT	\
	(AW_PID_2113_IIC_GEN_EN_DEFAULT_VALUE << AW_PID_2113_IIC_GEN_EN_START_BIT)

/* HOLDTH bit 7:0 (DACCFG4 0x0C) */
#define AW_PID_2113_HOLDTH_START_BIT	(0)
#define AW_PID_2113_HOLDTH_BITS_LEN	(8)
#define AW_PID_2113_HOLDTH_MASK	\
	(~(((1<<AW_PID_2113_HOLDTH_BITS_LEN)-1) << AW_PID_2113_HOLDTH_START_BIT))

#define AW_PID_2113_HOLDTH_RESERVED	(0)
#define AW_PID_2113_HOLDTH_RESERVED_VALUE	\
	(AW_PID_2113_HOLDTH_RESERVED << AW_PID_2113_HOLDTH_START_BIT)

#define AW_PID_2113_HOLDTH_DEFAULT_VALUE	(0x64)
#define AW_PID_2113_HOLDTH_DEFAULT	\
	(AW_PID_2113_HOLDTH_DEFAULT_VALUE << AW_PID_2113_HOLDTH_START_BIT)

/* default value of DACCFG4 (0x0C) */
/* #define AW_PID_2113_DACCFG4_DEFAULT		(0x1C64) */

/* DACST (0x20) detail */
/* BST_IPEAK_ST bit 15:12 (DACST 0x20) */
#define AW_PID_2113_BST_IPEAK_ST_START_BIT	(12)
#define AW_PID_2113_BST_IPEAK_ST_BITS_LEN	(4)
#define AW_PID_2113_BST_IPEAK_ST_MASK	\
	(~(((1<<AW_PID_2113_BST_IPEAK_ST_BITS_LEN)-1) << AW_PID_2113_BST_IPEAK_ST_START_BIT))

#define AW_PID_2113_BST_IPEAK_ST_DEFAULT_VALUE	(0)
#define AW_PID_2113_BST_IPEAK_ST_DEFAULT	\
	(AW_PID_2113_BST_IPEAK_ST_DEFAULT_VALUE << AW_PID_2113_BST_IPEAK_ST_START_BIT)

/* SPK_GAIN_ST bit 9:8 (DACST 0x20) */
#define AW_PID_2113_SPK_GAIN_ST_START_BIT	(8)
#define AW_PID_2113_SPK_GAIN_ST_BITS_LEN	(2)
#define AW_PID_2113_SPK_GAIN_ST_MASK	\
	(~(((1<<AW_PID_2113_SPK_GAIN_ST_BITS_LEN)-1) << AW_PID_2113_SPK_GAIN_ST_START_BIT))

#define AW_PID_2113_SPK_GAIN_ST_4_AV	(0)
#define AW_PID_2113_SPK_GAIN_ST_4_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_ST_4_AV << AW_PID_2113_SPK_GAIN_ST_START_BIT)

#define AW_PID_2113_SPK_GAIN_ST_6P0_AV	(1)
#define AW_PID_2113_SPK_GAIN_ST_6P0_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_ST_6P0_AV << AW_PID_2113_SPK_GAIN_ST_START_BIT)

#define AW_PID_2113_SPK_GAIN_ST_6P8P0_AV	(2)
#define AW_PID_2113_SPK_GAIN_ST_6P8P0_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_ST_6P8P0_AV << AW_PID_2113_SPK_GAIN_ST_START_BIT)

#define AW_PID_2113_SPK_GAIN_ST_12P0_AV	(3)
#define AW_PID_2113_SPK_GAIN_ST_12P0_AV_VALUE	\
	(AW_PID_2113_SPK_GAIN_ST_12P0_AV << AW_PID_2113_SPK_GAIN_ST_START_BIT)

#define AW_PID_2113_SPK_GAIN_ST_DEFAULT_VALUE	(3)
#define AW_PID_2113_SPK_GAIN_ST_DEFAULT	\
	(AW_PID_2113_SPK_GAIN_ST_DEFAULT_VALUE << AW_PID_2113_SPK_GAIN_ST_START_BIT)

/* ZERO_RST_SYNC bit 7 (DACST 0x20) */
#define AW_PID_2113_ZERO_RST_SYNC_START_BIT	(7)
#define AW_PID_2113_ZERO_RST_SYNC_BITS_LEN	(1)
#define AW_PID_2113_ZERO_RST_SYNC_MASK	\
	(~(((1<<AW_PID_2113_ZERO_RST_SYNC_BITS_LEN)-1) << AW_PID_2113_ZERO_RST_SYNC_START_BIT))

#define AW_PID_2113_ZERO_RST_SYNC_DEFAULT_VALUE	(0)
#define AW_PID_2113_ZERO_RST_SYNC_DEFAULT	\
	(AW_PID_2113_ZERO_RST_SYNC_DEFAULT_VALUE << AW_PID_2113_ZERO_RST_SYNC_START_BIT)

/* BSTVOUT_ST bit 6:0 (DACST 0x20) */
#define AW_PID_2113_BSTVOUT_ST_START_BIT	(0)
#define AW_PID_2113_BSTVOUT_ST_BITS_LEN	(7)
#define AW_PID_2113_BSTVOUT_ST_MASK	\
	(~(((1<<AW_PID_2113_BSTVOUT_ST_BITS_LEN)-1) << AW_PID_2113_BSTVOUT_ST_START_BIT))

#define AW_PID_2113_BSTVOUT_ST_3P25V	(0)
#define AW_PID_2113_BSTVOUT_ST_3P25V_VALUE	\
	(AW_PID_2113_BSTVOUT_ST_3P25V << AW_PID_2113_BSTVOUT_ST_START_BIT)

#define AW_PID_2113_BSTVOUT_ST_3P50V	(1)
#define AW_PID_2113_BSTVOUT_ST_3P50V_VALUE	\
	(AW_PID_2113_BSTVOUT_ST_3P50V << AW_PID_2113_BSTVOUT_ST_START_BIT)

#define AW_PID_2113_BSTVOUT_ST_3P75V	(2)
#define AW_PID_2113_BSTVOUT_ST_3P75V_VALUE	\
	(AW_PID_2113_BSTVOUT_ST_3P75V << AW_PID_2113_BSTVOUT_ST_START_BIT)

#define AW_PID_2113_BSTVOUT_ST_7P00V	(15)
#define AW_PID_2113_BSTVOUT_ST_7P00V_VALUE	\
	(AW_PID_2113_BSTVOUT_ST_7P00V << AW_PID_2113_BSTVOUT_ST_START_BIT)

#define AW_PID_2113_BSTVOUT_ST_DEFAULT_VALUE	(0)
#define AW_PID_2113_BSTVOUT_ST_DEFAULT	\
	(AW_PID_2113_BSTVOUT_ST_DEFAULT_VALUE << AW_PID_2113_BSTVOUT_ST_START_BIT)

/* default value of DACST (0x20) */
/* #define AW_PID_2113_DACST_DEFAULT		(0x0300) */

/* VBAT (0x21) detail */
/* VBAT_DET bit 9:0 (VBAT 0x21) */
#define AW_PID_2113_VBAT_DET_START_BIT	(0)
#define AW_PID_2113_VBAT_DET_BITS_LEN	(10)
#define AW_PID_2113_VBAT_DET_MASK	\
	(~(((1<<AW_PID_2113_VBAT_DET_BITS_LEN)-1) << AW_PID_2113_VBAT_DET_START_BIT))

#define AW_PID_2113_VBAT_DET_DEFAULT_VALUE	(0x263)
#define AW_PID_2113_VBAT_DET_DEFAULT	\
	(AW_PID_2113_VBAT_DET_DEFAULT_VALUE << AW_PID_2113_VBAT_DET_START_BIT)

/* default value of VBAT (0x21) */
/* #define AW_PID_2113_VBAT_DEFAULT		(0x0263) */

/* TEMP (0x22) detail */
/* TEMP_DET bit 9:0 (TEMP 0x22) */
#define AW_PID_2113_TEMP_DET_START_BIT	(0)
#define AW_PID_2113_TEMP_DET_BITS_LEN	(10)
#define AW_PID_2113_TEMP_DET_MASK	\
	(~(((1<<AW_PID_2113_TEMP_DET_BITS_LEN)-1) << AW_PID_2113_TEMP_DET_START_BIT))

#define AW_PID_2113_TEMP_DET_MINUS_40	(0x3D8)
#define AW_PID_2113_TEMP_DET_MINUS_40__VALUE	\
	(AW_PID_2113_TEMP_DET_MINUS_40 << AW_PID_2113_TEMP_DET_START_BIT)

#define AW_PID_2113_TEMP_DET_0	(0x00)
#define AW_PID_2113_TEMP_DET_0__VALUE	\
	(AW_PID_2113_TEMP_DET_0 << AW_PID_2113_TEMP_DET_START_BIT)

#define AW_PID_2113_TEMP_DET_1	(0x01)
#define AW_PID_2113_TEMP_DET_1__VALUE	\
	(AW_PID_2113_TEMP_DET_1 << AW_PID_2113_TEMP_DET_START_BIT)

#define AW_PID_2113_TEMP_DET_25	(0x19)
#define AW_PID_2113_TEMP_DET_25__VALUE	\
	(AW_PID_2113_TEMP_DET_25 << AW_PID_2113_TEMP_DET_START_BIT)

#define AW_PID_2113_TEMP_DET_55	(0x37)
#define AW_PID_2113_TEMP_DET_55__VALUE	\
	(AW_PID_2113_TEMP_DET_55 << AW_PID_2113_TEMP_DET_START_BIT)

#define AW_PID_2113_TEMP_DET_DEFAULT_VALUE	(0x019)
#define AW_PID_2113_TEMP_DET_DEFAULT	\
	(AW_PID_2113_TEMP_DET_DEFAULT_VALUE << AW_PID_2113_TEMP_DET_START_BIT)

/* default value of TEMP (0x22) */
/* #define AW_PID_2113_TEMP_DEFAULT		(0x0019) */

/* PVDD (0x23) detail */
/* PVDD_DET bit 9:0 (PVDD 0x23) */
#define AW_PID_2113_PVDD_DET_START_BIT	(0)
#define AW_PID_2113_PVDD_DET_BITS_LEN	(10)
#define AW_PID_2113_PVDD_DET_MASK	\
	(~(((1<<AW_PID_2113_PVDD_DET_BITS_LEN)-1) << AW_PID_2113_PVDD_DET_START_BIT))

#define AW_PID_2113_PVDD_DET_DEFAULT_VALUE	(0x263)
#define AW_PID_2113_PVDD_DET_DEFAULT	\
	(AW_PID_2113_PVDD_DET_DEFAULT_VALUE << AW_PID_2113_PVDD_DET_START_BIT)

/* default value of PVDD (0x23) */
/* #define AW_PID_2113_PVDD_DEFAULT		(0x0263) */

/* BOP_EN bit 5 (SADCCTRL3 0x3C) */
#define AW_PID_2113_BOP_EN_START_BIT	(5)
#define AW_PID_2113_BOP_EN_BITS_LEN	(1)
#define AW_PID_2113_BOP_EN_MASK	\
	(~(((1<<AW_PID_2113_BOP_EN_BITS_LEN)-1) << AW_PID_2113_BOP_EN_START_BIT))

#define AW_PID_2113_BOP_EN_ENABLE	(1)
#define AW_PID_2113_BOP_EN_ENABLE_VALUE	\
	(AW_PID_2113_BOP_EN_ENABLE << AW_PID_2113_BOP_EN_START_BIT)

#define AW_PID_2113_BOP_EN_DISABLE	(0)
#define AW_PID_2113_BOP_EN_DISABLE_VALUE	\
	(AW_PID_2113_BOP_EN_DISABLE << AW_PID_2113_BOP_EN_START_BIT)

/* CCO_MUX bit 6 (PLLCTRL1 0x54) */
#define AW_PID_2113_CCO_MUX_START_BIT	(6)
#define AW_PID_2113_CCO_MUX_BITS_LEN	(1)
#define AW_PID_2113_CCO_MUX_MASK	\
	(~(((1<<AW_PID_2113_CCO_MUX_BITS_LEN)-1) << AW_PID_2113_CCO_MUX_START_BIT))

#define AW_PID_2113_CCO_MUX_DIVIDED	(0)
#define AW_PID_2113_CCO_MUX_DIVIDED_VALUE	\
		(AW_PID_2113_CCO_MUX_DIVIDED << AW_PID_2113_CCO_MUX_START_BIT)

#define AW_PID_2113_CCO_MUX_BYPASS	(1)
#define AW_PID_2113_CCO_MUX_BYPASS_VALUE	\
	(AW_PID_2113_CCO_MUX_BYPASS << AW_PID_2113_CCO_MUX_START_BIT)


/* BSTCTRL1 (0x60) detail */
/* BST_RTH bit 13:8 (BSTCTRL1 0x60) */
#define AW_PID_2113_BST_RTH_START_BIT	(8)
#define AW_PID_2113_BST_RTH_BITS_LEN	(6)
#define AW_PID_2113_BST_RTH_MASK	\
	(~(((1<<AW_PID_2113_BST_RTH_BITS_LEN)-1) << AW_PID_2113_BST_RTH_START_BIT))

#define AW_PID_2113_BST_RTH_DEFAULT_VALUE	(4)
#define AW_PID_2113_BST_RTH_DEFAULT	\
	(AW_PID_2113_BST_RTH_DEFAULT_VALUE << AW_PID_2113_BST_RTH_START_BIT)

/* BST_MODE bit 7:6 (BSTCTRL1 0x60) */
#define AW_PID_2113_BST_MODE_START_BIT	(6)
#define AW_PID_2113_BST_MODE_BITS_LEN	(2)
#define AW_PID_2113_BST_MODE_MASK	\
	(~(((1<<AW_PID_2113_BST_MODE_BITS_LEN)-1) << AW_PID_2113_BST_MODE_START_BIT))

#define AW_PID_2113_BST_MODE_TRANSPARENT	(0)
#define AW_PID_2113_BST_MODE_TRANSPARENT_VALUE	\
	(AW_PID_2113_BST_MODE_TRANSPARENT << AW_PID_2113_BST_MODE_START_BIT)

#define AW_PID_2113_BST_MODE_FORCE_BOOST	(1)
#define AW_PID_2113_BST_MODE_FORCE_BOOST_VALUE	\
	(AW_PID_2113_BST_MODE_FORCE_BOOST << AW_PID_2113_BST_MODE_START_BIT)

#define AW_PID_2113_BST_MODE_CLASS_G	(2)
#define AW_PID_2113_BST_MODE_CLASS_G_VALUE	\
	(AW_PID_2113_BST_MODE_CLASS_G << AW_PID_2113_BST_MODE_START_BIT)

#define AW_PID_2113_BST_MODE_CLASS_H	(3)
#define AW_PID_2113_BST_MODE_CLASS_H_VALUE	\
	(AW_PID_2113_BST_MODE_CLASS_H << AW_PID_2113_BST_MODE_START_BIT)

#define AW_PID_2113_BST_MODE_DEFAULT_VALUE	(0x3)
#define AW_PID_2113_BST_MODE_DEFAULT	\
	(AW_PID_2113_BST_MODE_DEFAULT_VALUE << AW_PID_2113_BST_MODE_START_BIT)

/* BST_ATH bit 5:0 (BSTCTRL1 0x60) */
#define AW_PID_2113_BST_ATH_START_BIT	(0)
#define AW_PID_2113_BST_ATH_BITS_LEN	(6)
#define AW_PID_2113_BST_ATH_MASK	\
	(~(((1<<AW_PID_2113_BST_ATH_BITS_LEN)-1) << AW_PID_2113_BST_ATH_START_BIT))

#define AW_PID_2113_BST_ATH_DEFAULT_VALUE	(2)
#define AW_PID_2113_BST_ATH_DEFAULT	\
	(AW_PID_2113_BST_ATH_DEFAULT_VALUE << AW_PID_2113_BST_ATH_START_BIT)

/* default value of BSTCTRL1 (0x60) */
/* #define AW_PID_2113_BSTCTRL1_DEFAULT		(0x04C2) */

/* BSTCTRL2 (0x61) detail */
/* BST_IPEAK bit 15:12 (BSTCTRL2 0x61) */
#define AW_PID_2113_BST_IPEAK_START_BIT	(12)
#define AW_PID_2113_BST_IPEAK_BITS_LEN	(4)
#define AW_PID_2113_BST_IPEAK_MASK	\
	(~(((1<<AW_PID_2113_BST_IPEAK_BITS_LEN)-1) << AW_PID_2113_BST_IPEAK_START_BIT))

#define AW_PID_2113_BST_IPEAK_1P5A	(0)
#define AW_PID_2113_BST_IPEAK_1P5A_VALUE	\
	(AW_PID_2113_BST_IPEAK_1P5A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_1P75A	(1)
#define AW_PID_2113_BST_IPEAK_1P75A_VALUE	\
	(AW_PID_2113_BST_IPEAK_1P75A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_2P0A	(2)
#define AW_PID_2113_BST_IPEAK_2P0A_VALUE	\
	(AW_PID_2113_BST_IPEAK_2P0A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_2P25A	(3)
#define AW_PID_2113_BST_IPEAK_2P25A_VALUE	\
	(AW_PID_2113_BST_IPEAK_2P25A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_2P5A	(4)
#define AW_PID_2113_BST_IPEAK_2P5A_VALUE	\
	(AW_PID_2113_BST_IPEAK_2P5A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_2P75A	(5)
#define AW_PID_2113_BST_IPEAK_2P75A_VALUE	\
	(AW_PID_2113_BST_IPEAK_2P75A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_3P0A	(6)
#define AW_PID_2113_BST_IPEAK_3P0A_VALUE	\
	(AW_PID_2113_BST_IPEAK_3P0A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_3P25A	(7)
#define AW_PID_2113_BST_IPEAK_3P25A_VALUE	\
	(AW_PID_2113_BST_IPEAK_3P25A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_3P5A	(8)
#define AW_PID_2113_BST_IPEAK_3P5A_VALUE	\
	(AW_PID_2113_BST_IPEAK_3P5A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_3P75A	(9)
#define AW_PID_2113_BST_IPEAK_3P75A_VALUE	\
	(AW_PID_2113_BST_IPEAK_3P75A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_4A	(10)
#define AW_PID_2113_BST_IPEAK_4A_VALUE	\
	(AW_PID_2113_BST_IPEAK_4A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_4P25A	(11)
#define AW_PID_2113_BST_IPEAK_4P25A_VALUE	\
	(AW_PID_2113_BST_IPEAK_4P25A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_4P50A	(12)
#define AW_PID_2113_BST_IPEAK_4P50A_VALUE	\
	(AW_PID_2113_BST_IPEAK_4P50A << AW_PID_2113_BST_IPEAK_START_BIT)

#define AW_PID_2113_BST_IPEAK_DEFAULT_VALUE	(9)
#define AW_PID_2113_BST_IPEAK_DEFAULT	\
	(AW_PID_2113_BST_IPEAK_DEFAULT_VALUE << AW_PID_2113_BST_IPEAK_START_BIT)

/* BST_TDEG bit 11:8 (BSTCTRL2 0x61) */
#define AW_PID_2113_BST_TDEG_START_BIT	(8)
#define AW_PID_2113_BST_TDEG_BITS_LEN	(4)
#define AW_PID_2113_BST_TDEG_MASK	\
	(~(((1<<AW_PID_2113_BST_TDEG_BITS_LEN)-1) << AW_PID_2113_BST_TDEG_START_BIT))

#define AW_PID_2113_BST_TDEG_0P50_MS	(0)
#define AW_PID_2113_BST_TDEG_0P50_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_0P50_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_1P00_MS	(1)
#define AW_PID_2113_BST_TDEG_1P00_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_1P00_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_2P00_MS	(2)
#define AW_PID_2113_BST_TDEG_2P00_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_2P00_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_4P00_MS	(3)
#define AW_PID_2113_BST_TDEG_4P00_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_4P00_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_8P00_MS	(4)
#define AW_PID_2113_BST_TDEG_8P00_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_8P00_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_10P7_MS	(5)
#define AW_PID_2113_BST_TDEG_10P7_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_10P7_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_13P3_MS	(6)
#define AW_PID_2113_BST_TDEG_13P3_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_13P3_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_16P0_MS	(7)
#define AW_PID_2113_BST_TDEG_16P0_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_16P0_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_18P6_MS	(8)
#define AW_PID_2113_BST_TDEG_18P6_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_18P6_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_21P3_MS	(9)
#define AW_PID_2113_BST_TDEG_21P3_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_21P3_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_24P0_MS	(10)
#define AW_PID_2113_BST_TDEG_24P0_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_24P0_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_32P0_MS	(11)
#define AW_PID_2113_BST_TDEG_32P0_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_32P0_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_64P0_MS	(12)
#define AW_PID_2113_BST_TDEG_64P0_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_64P0_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_128_MS	(13)
#define AW_PID_2113_BST_TDEG_128_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_128_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_256_MS	(14)
#define AW_PID_2113_BST_TDEG_256_MS_VALUE	\
	(AW_PID_2113_BST_TDEG_256_MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_1024MS	(15)
#define AW_PID_2113_BST_TDEG_1024MS_VALUE	\
	(AW_PID_2113_BST_TDEG_1024MS << AW_PID_2113_BST_TDEG_START_BIT)

#define AW_PID_2113_BST_TDEG_DEFAULT_VALUE	(11)
#define AW_PID_2113_BST_TDEG_DEFAULT	\
	(AW_PID_2113_BST_TDEG_DEFAULT_VALUE << AW_PID_2113_BST_TDEG_START_BIT)

/* VOUT_VREFSET bit 6:0 (BSTCTRL2 0x61) */
#define AW_PID_2113_VOUT_VREFSET_START_BIT	(0)
#define AW_PID_2113_VOUT_VREFSET_BITS_LEN	(7)
#define AW_PID_2113_VOUT_VREFSET_MASK	\
	(~(((1<<AW_PID_2113_VOUT_VREFSET_BITS_LEN)-1) << AW_PID_2113_VOUT_VREFSET_START_BIT))

#define AW_PID_2113_VOUT_VREFSET_3P5V	(0)
#define AW_PID_2113_VOUT_VREFSET_3P5V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P5V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_3P5625V	(1)
#define AW_PID_2113_VOUT_VREFSET_3P5625V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P5625V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_3P625V	(2)
#define AW_PID_2113_VOUT_VREFSET_3P625V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P625V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_3P6875V	(3)
#define AW_PID_2113_VOUT_VREFSET_3P6875V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P6875V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_3P75V	(4)
#define AW_PID_2113_VOUT_VREFSET_3P75V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P75V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_3P8125V	(5)
#define AW_PID_2113_VOUT_VREFSET_3P8125V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_3P8125V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_11P4375V	(127)
#define AW_PID_2113_VOUT_VREFSET_11P4375V_VALUE	\
	(AW_PID_2113_VOUT_VREFSET_11P4375V << AW_PID_2113_VOUT_VREFSET_START_BIT)

#define AW_PID_2113_VOUT_VREFSET_DEFAULT_VALUE	(0x58)
#define AW_PID_2113_VOUT_VREFSET_DEFAULT	\
	(AW_PID_2113_VOUT_VREFSET_DEFAULT_VALUE << AW_PID_2113_VOUT_VREFSET_START_BIT)

/* default value of BSTCTRL2 (0x61) */
/* #define AW_PID_2113_BSTCTRL2_DEFAULT		(0x9B58) */

/* FORCE_PWM bit 12 (BSTCTRL3 0x62) */
#define AW_PID_2113_FORCE_PWM_START_BIT	(12)
#define AW_PID_2113_FORCE_PWM_BITS_LEN	(1)
#define AW_PID_2113_FORCE_PWM_MASK	\
	(~(((1<<AW_PID_2113_FORCE_PWM_BITS_LEN)-1) << AW_PID_2113_FORCE_PWM_START_BIT))

#define AW_PID_2113_FORCE_PWM_FORCEMINUS_PWM	(1)
#define AW_PID_2113_FORCE_PWM_FORCEMINUS_PWM_VALUE	\
	(AW_PID_2113_FORCE_PWM_FORCEMINUS_PWM << AW_PID_2113_FORCE_PWM_START_BIT)

#define AW_PID_2113_FORCE_PWM_BURST	(0)
#define AW_PID_2113_FORCE_PWM_BURST_VALUE	\
	(AW_PID_2113_FORCE_PWM_BURST << AW_PID_2113_FORCE_PWM_START_BIT)

/* BST_OS_WIDTH bit 2:0 (BSTCTRL5 0x64) */
#define AW_PID_2113_BST_OS_WIDTH_START_BIT	(0)
#define AW_PID_2113_BST_OS_WIDTH_BITS_LEN	(3)
#define AW_PID_2113_BST_OS_WIDTH_MASK	\
	(~(((1<<AW_PID_2113_BST_OS_WIDTH_BITS_LEN)-1) << AW_PID_2113_BST_OS_WIDTH_START_BIT))


#define AW_PID_2113_BST_OS_WIDTH_50NS	(4)
#define AW_PID_2113_BST_OS_WIDTH_50NS_VALUE	\
	(AW_PID_2113_BST_OS_WIDTH_50NS << AW_PID_2113_BST_OS_WIDTH_START_BIT)

/* BST_LOOPR bit 1:0 (BSTCTRL6 0x65) */
#define AW_PID_2113_BST_LOOPR_START_BIT	(0)
#define AW_PID_2113_BST_LOOPR_BITS_LEN	(2)
#define AW_PID_2113_BST_LOOPR_MASK	\
	(~(((1<<AW_PID_2113_BST_LOOPR_BITS_LEN)-1) << AW_PID_2113_BST_LOOPR_START_BIT))

#define AW_PID_2113_BST_LOOPR_340K	(2)
#define AW_PID_2113_BST_LOOPR_340K_VALUE	\
	(AW_PID_2113_BST_LOOPR_340K << AW_PID_2113_BST_LOOPR_START_BIT)

/* RSQN_DLY bit 15:14 (BSTCTRL7 0x66) */
#define AW_PID_2113_RSQN_DLY_START_BIT	(14)
#define AW_PID_2113_RSQN_DLY_BITS_LEN	(2)
#define AW_PID_2113_RSQN_DLY_MASK	\
	(~(((1<<AW_PID_2113_RSQN_DLY_BITS_LEN)-1) << AW_PID_2113_RSQN_DLY_START_BIT))

#define AW_PID_2113_RSQN_DLY_35NS	(2)
#define AW_PID_2113_RSQN_DLY_35NS_VALUE	\
	(AW_PID_2113_RSQN_DLY_35NS << AW_PID_2113_RSQN_DLY_START_BIT)

/* BURST_SSMODE bit 3 (BSTCTRL8 0x67) */
#define AW_PID_2113_BURST_SSMODE_START_BIT	(3)
#define AW_PID_2113_BURST_SSMODE_BITS_LEN	(1)
#define AW_PID_2113_BURST_SSMODE_MASK	\
	(~(((1<<AW_PID_2113_BURST_SSMODE_BITS_LEN)-1) << AW_PID_2113_BURST_SSMODE_START_BIT))

#define AW_PID_2113_BURST_SSMODE_FAST	(0)
#define AW_PID_2113_BURST_SSMODE_FAST_VALUE	\
	(AW_PID_2113_BURST_SSMODE_FAST << AW_PID_2113_BURST_SSMODE_START_BIT)

/* BST_BURST bit 9:7 (BSTCTRL9 0x68) */
#define AW_PID_2113_BST_BURST_START_BIT	(7)
#define AW_PID_2113_BST_BURST_BITS_LEN	(3)
#define AW_PID_2113_BST_BURST_MASK	\
	(~(((1<<AW_PID_2113_BST_BURST_BITS_LEN)-1) << AW_PID_2113_BST_BURST_START_BIT))

#define AW_PID_2113_BST_BURST_30MA	(2)
#define AW_PID_2113_BST_BURST_30MA_VALUE	\
	(AW_PID_2113_BST_BURST_30MA << AW_PID_2113_BST_BURST_START_BIT)

/* EF_ISN_GESLP_H bit 9:0 (EFRH4 0x78) */
#define AW_PID_2113_EF_ISN_GESLP_H_START_BIT	(0)
#define AW_PID_2113_EF_ISN_GESLP_H_BITS_LEN	(10)
#define AW_PID_2113_EF_ISN_GESLP_H_MASK	\
	(~(((1<<AW_PID_2113_EF_ISN_GESLP_H_BITS_LEN)-1) << AW_PID_2113_EF_ISN_GESLP_H_START_BIT))

/* EF_VSN_GESLP_H bit 9:0 (EFRH3 0x79) */
#define AW_PID_2113_EF_VSN_GESLP_H_START_BIT	(0)
#define AW_PID_2113_EF_VSN_GESLP_H_BITS_LEN	(10)
#define AW_PID_2113_EF_VSN_GESLP_H_MASK	\
	(~(((1<<AW_PID_2113_EF_VSN_GESLP_H_BITS_LEN)-1) << AW_PID_2113_EF_VSN_GESLP_H_START_BIT))

/* EF_ISN_GESLP_L bit 9:0 (EFRL4 0x7C) */
#define AW_PID_2113_EF_ISN_GESLP_L_START_BIT	(0)
#define AW_PID_2113_EF_ISN_GESLP_L_BITS_LEN	(10)
#define AW_PID_2113_EF_ISN_GESLP_L_MASK	\
	(~(((1<<AW_PID_2113_EF_ISN_GESLP_L_BITS_LEN)-1) << AW_PID_2113_EF_ISN_GESLP_L_START_BIT))

/* EF_VSN_GESLP_L bit 9:0 (EFRL3 0x7D) */
#define AW_PID_2113_EF_VSN_GESLP_L_START_BIT	(0)
#define AW_PID_2113_EF_VSN_GESLP_L_BITS_LEN	(10)
#define AW_PID_2113_EF_VSN_GESLP_L_MASK	\
	(~(((1<<AW_PID_2113_EF_VSN_GESLP_L_BITS_LEN)-1) << AW_PID_2113_EF_VSN_GESLP_L_START_BIT))


/* detail information of registers end */

/********************************************
 * Efdbmd
 *******************************************/
#define AW_PID_2113_EF_DBMD_MASK		(0xfff7)
#define AW_PID_2113_AND_VALUE			(0x0000)
#define AW_PID_2113_OR_VALUE			(0x0008)

/********************************************
 * Volume Coefficient
 *******************************************/
#define AW_PID_2113_VOL_STEP		(6 * 8)
/********************************************
 * Vcalb
 *******************************************/
#define AW_PID_2113_EF_VSN_GESLP_SIGN_MASK	(~0x0200)
#define AW_PID_2113_EF_VSN_GESLP_NEG		(~0xfc00)

#define AW_PID_2113_EF_ISN_GESLP_SIGN_MASK	(~0x0200)
#define AW_PID_2113_EF_ISN_GESLP_NEG		(~0xfc00)

#define AW_PID_2113_CABL_BASE_VALUE		(1000)
#define AW_PID_2113_ICABLK_FACTOR		(1)
#define AW_PID_2113_VCABLK_FACTOR		(1)

#define AW_PID_2113_VCAL_FACTOR			(1<<13)

#define AW_PID_2113_ICALK_SHIFT			(0)
#define AW_PID_2113_ICALKL_SHIFT		(0)
#define AW_PID_2113_VCALK_SHIFT			(0)
#define AW_PID_2113_VCALKL_SHIFT		(0)

#define AW_PID_2113_MONITOR_VBAT_RANGE		(6025)
#define AW_PID_2113_MONITOR_INT_10BIT		(1023)
#define AW_PID_2113_MONITOR_TEMP_SIGN_MASK	(~(1<<9))
#define AW_PID_2113_MONITOR_TEMP_NEG_MASK	(0xFC00)

#define AW_PID_2113_TEMH_MASK			(0x83ff)
#define AW_PID_2113_TEML_MASK			(0x83ff)
#define AW_PID_2113_DEFAULT_CFG			(0x0000)
/********************************************
 * Init check
 *******************************************/
#define AW_PID_2113_INIT_CHECK_REG		(0x73)
#define AW_PID_2113_INIT_CHECK_VALUE		(0x1D40)

/********************************************
 * Dither
 *******************************************/
#define AW_PID_2113_DITHER_START_BIT	(14)
#define AW_PID_2113_DITHER_BITS_LEN	(1)
#define AW_PID_2113_DITHER_MASK	\
	(~(((1<<AW_PID_2113_DITHER_BITS_LEN)-1) << AW_PID_2113_DITHER_START_BIT))

#define AW_PID_2113_DITHER_DISABLE	(0)
#define AW_PID_2113_DITHER_DISABLE_VALUE	\
	(AW_PID_2113_DITHER_DISABLE << AW_PID_2113_DITHER_START_BIT)

#define AW_PID_2113_DITHER_ENABLE	(1)
#define AW_PID_2113_DITHER_ENABLE_VALUE	\
	(AW_PID_2113_DITHER_ENABLE << AW_PID_2113_DITHER_START_BIT)

#endif  /* #ifndef  __AW_PID_2113_REG_H__ */
